Verilog/Concept HDL Direct Naming Conventions

Verilog requires that you follow several rules for user-specified names in Xilinx designs. Additionally, the Xilinx/Cadence interface requires that you use HDL Direct methodology: therefore, you must adhere to these rules when naming objects in your Concept schematics. The following list details rules for Verilog naming.

• A Verilog name consists of a sequence of letters, digits, dollar signs ($), and the underscore (_) symbol. Verilog allows only the following characters in names.
  
  a-z, A-Z, 0-9, _, and $
  
  
• You cannot use a digit or $ as a first character of a name. The name must begin with a letter or an underscore. Designs entered in Concept require a letter as the first character in a name.
  
  
• Names are case sensitive (unless you use the upper case option when compiling).
  
  
• Names cannot exceed a length of 1024 characters. The following are examples of valid names.
  
  adder
  bus_b
  _signal1
  n$777
  clockin
  
  
• You cannot use Verilog keywords as user-specified names. This includes Verilog reserved words like “input,” “output,” and “module.”
  
  
• Concept allows identical block names and signal names, but Verilog, does not.
  
  

For more information, refer to section 2.5 in the Verilog-XL Reference Manual.