Post-Implementation Timing Simulation

You can perform a post-implementation timing simulation on both FPGA and CPLD designs. For FPGAs, you must first map, route, and back-annotate your design. For CPLDs, you must run the design through the CPLD fitter.

NOTE

Post-implementation timing simulation for FPGAs is also referred to as post-route timing simulation.

The next figure illustrates the design flow for post-implementation timing simulation.

Figure 6.3 Post-Implementation Timing Simulation

Running NGD2VER

The NGD2VER program translates your design into a Verilog HDL file containing a netlist description of the design in terms of Xilinx simulation primitives. You then use the Verilog file to perform a simulation with the Cadence Verilog-XL simulator. You must use NGD2VER with the -tf and -ul options to create the appropriate files for use with the Cadence Verilog-XL simulator.

The following syntax translates your design to a Verilog file.

ngd2ver [-tf] -ul -pf infile[.nga] [outfile.v]

• The -tf option generates a testbench file. The file has a .tv extension. You must make a copy of this testbench template and edit it by adding your simulation vectors, For an example of a testbench template file, see the annotated example in the “Sample Test Fixture - XC4000EX Post-NGDBuild Simulation (GSR and GTS simulation)” section of the “Files” appendix.
  
  
• The -ul option causes NGD2VER to write a `uselib library directive into the output Verilog file. The path writes as shown below to point to the Verilog SIMPRIM library.
  
  `uselib dir=$XILINX/verilog/src/simprims libext=.vmd
  
  $XILINX is the location of the Xilinx software and $XILINX/verilog/src/simprims is the location of the Verilog SIMPRIM library.
  
  
• The -pf option writes out a pin file (a Cadence signal-to-pin mapping file). NGD2VER generates a PIN file if the input file contains routed external pins and you specified a -pf command line option. Use this file (with a .pin extension) as an input to XIL2CDS. If you need to run XIL2CDS you must specify this option.
  
  
• infile is the input NGA file. If you enter a file name with no extension, NGD2VER automatically searches for a file with the name you specified plus a .nga extension.
  
  
• outfile indicates the filename to which the output of NGD2VER writes and the default is infile.v (with infile the same root name as the input file).
  
  

NGD2VER also generates an SDF file containing delays obtained from the fully-implemented input file. NGD2VER only generates an SDF file if the input is an NGA file which contains timing information. The SDF file generated by NGD2VER is based on SDF version 2.1.

NOTE

Use the produced SDF file solely with the Verilog file generated by NGD2VER. Do not attempt to use the SDF file in conjunction with the original design or the product of another netlist writer.

The Cadence command XIL2CDS uses the PIN, PKG, SDF, and V files output files to generate the following files.

• A chips_prt file containing physical information about the component
  
  
• A body file (a Concept symbol file)
  
  

XIL2CDS enables you to integrate your chip-level design into a board level schematic.