Post-Map Timing Simulation (FPGAs)

You can optionally perform post-map timing simulation for FPGAs. The post-MAP simulation gives you a rough idea of whether your design can meet timing requirements before adding delays due to routing.

NOTE

After mapping, either perform a static timing analysis using TRCE, or conduct a post-map simulation. You can often run a static timing analysis faster than a simulation, especially useful for first-time designs. Refer to the Xilinx Development System Reference Guide for information about running static timing analysis. Conversely, if a testbench file for post-NGDBuild functional simulation already exists, you can use that testbench file for post-MAP and post-implementation timing simulation (minor modifications may be required).

The following figure provides a flow chart of post-map simulation.

Figure 6.1 Post-Map Timing Simulation

Mapping and Back-Annotation

To perform a post-map simulation, you must have previously mapped and back-annotated your design. To perform mapping and back-annotation, use the MAP and NGDAnno commands as follows.

map design.ngd

ngdanno design.ncd design.ngm

For details on mapping and back-annotation, see the following chapters in the Development System Reference Guide.

• ”MAP - The Technology Mapper” chapter
  
  
• “NGDAnno” chapter
  
  

Back-annotation distributes physical design information, including timing delays, back to the logical design for simulation.

In the Xilinx Development System, back-annotation for FPGA designs functions as described below.

• The NGDAnno program distributes delays, setup and hold times, and pulse widths found in the physical NCD design file onto the logical design view represented in the NGD file. Physical component locations for PADs are also combined with the information in the NGD file.
  
  NGDAnno produces as output an NGA file containing the logical design with annotations.
  
  
• The annotated design NGA file serves as an input to the netlist writer NGD2VER, which translates the back-annotated information into a Verilog netlist for simulation.
  
  

Running NGD2VER

The NGD2VER program translates your design into a Verilog HDL file containing a netlist description of the design in terms of Xilinx simulation primitives (SIMPRIMS). You then use the Verilog file to perform a simulation with the Cadence Verilog-XL simulator. You must use NGD2VER with the -tf and -ul options to create the appropriate files for use with the Cadence Verilog-XL simulator.

NGD2VER also generates a version 2.1 SDF file containing delays obtained from the fully-implemented input file. NGD2VER only generates an SDF file if the input is an NGA file, which contains timing information.

Use the produced SDF file solely with the Verilog file generated by NGD2VER. Do not attempt to use the SDF file in conjunction with the original design or the product of another netlist writer. The following shows the recommended procedure using NGD2VER.

ngd2ver -tf -ul design.nga

cp design.tv designt.stim

Edit designt.stim and add your test vectors.

The following syntax translates your design to a Verilog file.

ngd2ver [-tf] -ul infile[.nga] [outfile.v]

• The -tf option generates a testbench template file with a .tv extension. Copy this testbench template to a file named designt.stim, then edit this .stim file and add your simulation vectors.
  
  For an example of a testbench template file, see the annotated example in the “Sample Test Fixture - XC4000EX Post-NGDBuild Simulation (GSR and GTS simulation)” section of the “Files” appendix.
  
  
• The -ul option causes NGD2VER to write a `uselib library directive into the output Verilog file. The path writes as shown below to point to the Verilog SIMPRIM library.
  
  `uselib dir=$XILINX/verilog/src/simprims libext=.vmd
  
  $XILINX is the location of the Xilinx software, and $XILINX/verilog/data is the location of the Verilog SIMPRIM library.
  
  
• infile is the input NGA file. If you enter a file name with no extension, NGD2VER automatically looks for a file with the name you specified plus a .nga extension.
  
  
• outfile indicates the filename to which the output of NGD2VER writes. Default is infile.v (with infile the same root name as the input file).
  
  

See the “Setting Global Set/Reset and Tri-state Signals (FPGAs)” section of the “Design and Simulation Techniques” chapter for information on driving the global signals GSR, GR, GTS and PRLD.

Running the Verilog Timing Simulation

Make sure you edit a copy (designt.stim) of the testbench stimulus template to create a user-specified testbench file.

cp design.tv designt.stim

edit designt.stim

You can replace the above edit command with your favorite text editor.

See the “Files” appendix for an example of a testbench template. The example is only a template; it does not contain test vectors.

To simulate the design with Verilog-XL, you must specify the full pathname of the following files.

• The design Verilog netlist (designt.v)
  
  
• A copy of the testbench file (designt.tv) named designt.stim
  
  

The following shows the syntax of the command.

verilog full_path_to_design_namet.stim \ full_path_to_design_namet.v

(The “\”at the end of a line indicates that the line following the current one can be typed on the same command line.)

If available, specify the +gui option to invoke the Verilog Environment.

The next figure illustrates the Verilog-XL Control Window (VCW) that displays when you use the +gui option.

Figure 6.2 The Verilog Environment (+gui)

To conveniently run a Verilog simulation, create a script containing a command line with all the required options. To run a simulation, simply invoke the script as shown in the following example.

For a design named “calc” targeting an XC4000EX component, assume you generate a Verilog netlist called “calct.v” and create a testbench file called “calct.tv.” Make a copy of “calct.tv” named “calct.stim” and add your stimulus to this file.

To run a timing simulation, use this command line.

verilog xilinx.run/calct.stim xilinx.run/calct.v

To invoke SimWave do one of the following.

• Enter the following command.
  
  simwave &
  
  
• Click the Waveform View button in the Verilog -XL GUI.
  
  

For a complete description of SimWave, refer to the “Using SimWave” section of the “Schematic Design Tutorial” chapter.

Global Reset

Always toggle global reset at the beginning of a simulation to ensure that all flip-flops and latches initialize to a known state. See the “Setting Global Set/Reset and Tri-state Signals (FPGAs)” section of the “Design and Simulation Techniques” chapter for information on toggling global reset for XC3000A/L, XC3100A/L, XC4000/E/EX/XL/XV, XC5200, XC9500/XL, and Spartan/XL devices.