You can enter specific blocks of your design in some form other than Concept schematics, such as HDL, or other third-party formats. However, whatever form of entry you use for a design block, you must convert it into one of the following formats before you can incorporate it into your Concept schematic: NGO, V, XNF or EDIF. Only Cadence supports incorporating a Verilog (V) behavioral description into your Concept schematic.
To incorporate these netlist files into your schematic, you must create a body for the netlist file and place it on your schematic as you would any other component. For a description of how to generate a body for a design block, refer to the “Creating Bodies for Non-Schematic Design Blocks” section of the “Design Entry” chapter.
