The following subsections describe XC9500 flip-flop initialization.
XC9500 devices do not contain IOB flip-flops.
To set the initial value of XC9500 macrocell flip-flops at power-up in your simulation, follow these instructions.
For Unified Library and post-NGDBuild functional simulation, you must explicitly drive the macrocell flip-flops High or Low in your test fixture file.
For timing simulation, set the macrocell flip-flops to power up either High or Low on power-up by attaching the appropriate INIT property (“S” for “SET” and “R” for “RESET”) to each macrocell flip-flop in your schematic. The default value of INIT is R (Reset). When you activate the global preload signal (PRLD) during a timing simulation, the macrocell flip-flops initialize to the assigned value.
