Setting Global Set/Reset and Tri-state Signals (FPGAs)

How you set the global set/reset, global reset and global tri-state signals depends on which flow you use (Cadence Concept HDL Direct, or other), the part type you use, and whether your design contains a STARTUP component (Spartan/XL, XC4000E/L/EX/XL/XV, and XC5200 devices only). The following subsections describe the various approaches.

Setting Global Set/Reset

At the beginning of an FPGA design simulation, you must toggle the global set/reset signal (GSR in Spartan/XL and XC4000E/L/EX/XL/XV designs), or the GR global reset signal in XC5200 or XC3000A/L and XC3100A/L designs. Toggling the global set/reset emulates the power-on reset of the FPGA. If you do not toggle, the flip-flops and latches in your simulation can function incorrectly.

The global set/reset net is present in the implemented design whether or not you instantiate the STARTUP block in your design. STARTUP gives you the option to control the global reset net from an external pin.

You can select the global set/reset pulse width so that it reflects the actual amount of time it takes for the chip to go through the reset process after power up occurs (T_mrw or T_por). Refer to The Programmable Logic Data Book for this information about the appropriate device.

The general procedure for specifying global set/reset or global reset during a pre-NGDBuild Verilog Unified Library simulation involves defining the global reset signals with one of the following Verilog macros: GSR_SIGNAL or GR_SIGNAL. These global nets do not exist in the Concept Unified Libraries, and as a result, also do not exist in a netlist generated directly from Concept schematics processed only by running CONCEPT2XIL with the -sim_only option. In addition, you must also declare the global set/reset signal either as a Verilog wire or reg. Your choice of wire or reg depends on whether the design contains a STARTUP component.

NOTE

The Xilinx M1.4 and later releases use the Verilog Unified Library only in pre-NGDBuild simulation of Cadence Concept or Concept/LogiBlox mixed-mode designs immediately after running CONCEPT2XIL with the -sim_only option. Simulation at all other points of the flow utilizes the Verilog SIMPRIM Libraries.

For pre-NGDBuild Unified Library functional simulation, you must set the value of the appropriate Verilog macro (GSR_SIGNAL or GR_SIGNAL) to the name of the GSR or GR net, qualified by the appropriate scope identifiers. (The Verilog Unified Libraries use GSR_SIGNAL and GR_SIGNAL to emulate the global reset signals.) The scope identifiers consist of some combination of the test module scope and the design instance scope. You must use the scope qualifiers because the Verilog Unified Library simulation models emulate a global reset signal by interpreting the GSR_SIGNAL and GR_SIGNAL macros, which require the scope qualifiers.

The net name you specify, and whether you specify the net as a Verilog reg or a wire, depends on whether or not you instantiated a STARTUP block in the design.

1. If the design lacks a STARTUP block, name the global (set/)reset net test.GSR or test.GR (remember that Verilog is case-sensitive), and declare the signal as a Verilog reg data type.
   
   
2. If the design contains a STARTUP block and the GSR pin connects to a net, set the value of GSR_SIGNAL to the net connected to the GSR pin on the STARTUP symbol.
   
   You actually toggle, at the beginning of the simulation, the port or signal in the design used to control global set/reset, usually an external input port in the Verilog netlist. You can make this signal a wire if logic internal to your design controls global reset.
   
   
3. When invoking Verilog-XL to run the simulation, you must specify the testbench file before the Verilog netlist for the design in order for the simulation to work properly.
   
   For example, enter the following for Unified Library simulation.
   
   verilog design.stim design.v -f design.vf
   
   For example, enter the following for post-NGDBuild functional simulation.
   
   verilog design.stim designf.v
   
   
4. Name the main module in the testbench “test” in a manner consistent with the name of the testbench module written out downstream in the design flow by NGD2VER when you do post-NGDBuild, post-MAP, or post-route simulation. Maintaining this naming consistency allows you to use the same testbench file for simulation at all stages of the design flow with minimal modification.
   
   

NOTE

For Unified Library functional simulation, you must always define the appropriate Verilog macro (GSR_SIGNAL or GR_SIGNAL) for the global set/reset signal. This macro is not used in timing simulation when the design contains a STARTUP block.

NOTE

The GSR signal in Spartan/XL and XC4000E/L/EX/XL/XV devices and the GR signal in XC5200 devices is active High, whereas the GR signal (XC3000A/L and XC3100A/L designs) signal is active Low.

NOTE

For post-NGDBuild and post-route timing simulation, the testbench template (TV file) produced by running NGD2VER with the -tf option already contains most of the code described previously (and illustrated in the following examples) for defining and toggling GSR or GR.

Designs with No STARTUP Block

When the design lacks a STARTUP block, you can use the same testbench file with little or no modification at all stages of the design flow if you follow these guidelines.

The following illustrates how you can drive the GSR signal in a Verilog-XL testbench file at the beginning of a pre-NGDBuild Unified Library functional simulation.

NOTE

This document uses the terms “testbench” and “test fixture” synonymously.

Reference the global set/reset net as “GSR” in a Spartan/XL or XC4000E/L/EX/XL/XV design when the design lacks a STARTUP block. Name the Verilog macro defining the global net “GSR_SIGNAL” to make it consistent with how the Verilog Unified Simulation Library models it.

• Within the testbench file, declare GSR as a Verilog register within the “test” module.
  
  module test;

reg GSR;
  
  
• Set a macro called GSR_SIGNAL to test.GSR (the name of the global set/reset signal, qualified by the name of the testbench module) using the `define compiler directive.
  
  

`define GSR_SIGNAL test.GSR;

Toggle GSR High, then Low in an “initial” block.

   module test;

   reg GSR;

   `define GSR_SIGNAL test.GSR;

   initial

     begin

        GSR = 1;       // reset the device

        #100 GSR = 0;

In this example, the active High GSR signal in the Spartan/XL or XC4000E/L/EX/XL/XV device activates by driving it later, it deactivates by driving it Low. (100 ns is an arbitrarily chosen value.)

Alternatively, you can reference the macros instead of the “GSR” signal name in the initial block.

   initial

     begin

        `GSR_SIGNAL = 1;       // reset the device

        #100 `GSR_SIGNAL = 0;

You can use the same test fixture for simulating at other stages of the design flow when the design lacks a STARTUP block.

For pre-NGDBuild Unified Library functional simulation, simulate the active High GR net in XC5200 devices in the same manner as GSR for Spartan/XL or XC4000E/L/EX/XL/XV. Substituting GR for GSR and GR_SIGNAL for GSR_SIGNAL gives the following.

   module test;

   reg GR;

   `define GR_SIGNAL test.GR;

   initial

     begin

         `GR_SIGNAL = 1;      // reset the device

        #100 `GR_SIGNAL = 0;

You can also use the same test fixture for simulating your design at other stages of the design flow when the design lacks a STARTUP block.

Asserting global reset in XC3000A/L and XC3100A/L designs uses an almost identical procedure for asserting global reset in XC5200 designs, except that GR in XC3000A/L and XC3100A/L devices is active Low. However, XC3000A/L and XC3100A/L devices do not support the STARTUP block.

   module test;

   reg GR;

   `define GR_SIGNAL test.GR; 

   initial

     begin

         `GR_SIGNAL = 0;     // reset the device

        #100 `GR_SIGNAL = 1;

NOTE

Unified Library functional simulation netlists and SIMPRIM library based netlists generated by NGD2VER model the Global Reset (GR) signal in the XC3000A/L and XC3100A/L architecture differently. The Verilog Unified Library models GR as a wire within a global module, while a SIMPRIM-based netlist always models the GR as an external port. As a result, you cannot use the same testbench file to do both Unified library simulation and SIMPRIM-based simulation.

Designs With STARTUP block (Spartan/XL, XC4000E/L/EX/XL/XV and XC5200 Devices Only)

Two distinct differences exist between asserting global set/reset in a design containing the STARTUP block and a design without a STARTUP block. First, in the design with the STARTUP block, the `define statement must specify the name of the net attached to the GSR pin (Spartan/XL or XC4000E/L/EX/XL/XV devices) or GR pin (XC5200 devices) on the STARTUP block.

`define GSR_SIGNAL net_connected_to_GSR_pin

Secondly, you toggle the external input signal “GSR_user_control_signal” connected to the STARTUP block. If the signal is a user-specified external input as shown in the next illustration, it appears in your Verilog netlist as an input port. You drive it as follows.

   initial 
   begin 
      GSR_user_control_signal = 1;
      #100 GSR_user_control_signal = 0;

Figure 7.1 User-specified External Input Signal

The following example shows how to drive the global set/reset signal in a Verilog-XL test fixture file at the beginning of a pre-NGDBuild Unified Library functional simulation when a Spartan/XL or XC4000E/L/EX/XL/XV design contains a STARTUP block.

In the following illustration, a signal called “mygsr” is the GSR_user_control_signal. In this case “mygsr,” an external user signal that controls GSR, sources an IBUF, which in turn sources a signal called “gsrin.” “gsrin” represents the net_connected_to_GSR_pin - the pin that directly sources the GSR pin of the STARTUP block.

Figure 7.2 GSR_user_control_signal “mygsr”

• The design allows you to control global set/reset in the device by driving the external input port, “mygsr.” In the test fixture file, “mygsr” appears as a Verilog reg within the “test” module.
  
  module test;
  reg mygsr;
  
  
• In addition, for Spartan/XL or XC4000E/L/EX/XL/XV designs, declare a Verilog macro called GSR_SIGNAL to make the connection between the user logic and the global GSR net embedded in the Unified Library models. Use a `define directive to set GSR_SIGNAL to the following.
  
  test_module_name.design_instance_name.gsr_pin_signal
  
  gsr_pin_signal corresponds to the name of the signal connected to the GSR pin on the STARTUP block (in this case, “gsrin.” The scope qualifier in this case also includes the name of the design instance (“uut”) in anticipation that the net appears as an internal net of the design in the post-NGDBuild, post-Map and post-route simulations further down in the flow.
  
  `define GSR_SIGNAL test.uut.gsrin;
  
  
• Toggle the global set/reset control signal High, then Low in an “initial” block.
  
  

   module test;
     reg mygsr;
      `define GSR_SIGNAL test.uut.gsrin;

   initial
     begin
        mygsr = 1;      // reset the device
        #100 mygsr = 0;

Post-NGDBuild functional simulation, post-Map timing simulation, and post-route timing simulation use a procedure identical to Unified Library functional simulation.

For an XC5200 design containing a STARTUP block (similar to the previous Example 1 for Spartan/XL and XC4000 designs), simulate the net controlling GR in the same manner as for Spartan/XL and XC4000E/L/EX/XL/XV.

Substitute GR_SIGNAL for GSR_SIGNAL, mygr for mygsr, and gr_in for gsr_in in Example 1 to obtain the test fixture fragment for stimulating GR in a Verilog Unified Library simulation.

Figure 7.3 Substituting GR_SIGNAL for GSR_SIGNAL

   module test;
     reg mygr;
   
     `define GR_SIGNAL test.uut.gr_in;

   initial
     begin
        mygr = 1;      // reset the device
        #100 mygr = 0;

Post-NGDBuild functional simulation, post-Map timing simulation, and post-route timing simulation use the procedure identical to Unified Library functional simulation, except that you must omit the `define statement for GR_SIGNAL.

XC3000A/L and XC3100A/L designs do not support STARTUP. Follow the procedure for XC3000A/L and XC3100A/L designs without STARTUP blocks.

Setting Global Tri-state (Spartan, XC4000 and XC5200 Outputs Only)

Spartan/XL, XC4000E/L/EX/XL/XV, and XC5200 devices use a global control signal (GTS) that tri-states all output pins. This capability allows you to isolate the actual part during board level testing. You can also tri-state the FPGA device outputs during board level simulation to assist in simulation debug. In most cases, however, GTS usually deactivates, making the outputs active.

Although the STARTUP component gives you the option of controlling the global tri-state net from an external pin, more often than not it only controls global reset. In this case, leave the GTS pin unconnected at the design entry phase; the GTS pin floats to its inactive state level. An implemented design contains a global tri-state GTS pin whether or not a STARTUP block instantiates. If desired, explicitly deactivate GTS by driving it Low in your test fixture file, or connecting the GTS pin to GND in your input design.

Specifying GTS uses a general procedure similar to that used for specifying the global set/reset signals GSR and GR. Define the global tri-state signal with the Verilog macro, GTS_SIGNAL. You use this macro because the global net is not modeled in a netlist generated directly from Concept schematics, so far processed only by running CONCEPT2XIL with the -sim_only option. In addition, you must also declare the global tri-state signal either as a Verilog wire or reg. Your choice of wire or reg depends on whether the design contains a STARTUP component.

The specific net name you specify, and whether you specify the net as a Verilog reg or a wire, depends on whether or not you instantiated a STARTUP block in the design, and whether you connected a signal to the STARTUP GTS pin.

1. If the design contains no STARTUP block, name the global tri-state net test.GTS (remember that Verilog is case-sensitive), and declare the signal as a Verilog reg data type.
   
   
2. If the design contains a STARTUP block and the GTS pin connects to a net, set the value of GTS_SIGNAL to the name of the net connected to the GTS pin on the STARTUP symbol. You actually toggle, at the beginning of the simulation, the port or signal in the design used to control global tri-state, usually an external input port in the Verilog netlist. Alternatively, you can toggle a wire if internal logic controls global tri-state in your design.
   
   
3. Name the main module in the testbench file “test” for consistency with the name of the test fixture module written out downstream in the design flow by NGD2VER when you do post-NGDBuild, post-Map (optional) and post-route simulation. If you maintain this naming consistency, you can use the same test fixture file for simulation at all stages of the design flow with minimal modification.
   
   

NOTE

For Unified Library functional simulation, you must always define the appropriate Verilog macro (GTS_SIGNAL).

NOTE

The GTS signal in Spartan/XL, XC4000E/L/EX/XL/XV, and XC5200 devices is active High. You do not need this macro in timing simulation when the design contains a STARTUP block with the GTS pin connected.

NOTE

For post-NGDBuild and post-route timing simulation, the testbench template (TV file) produced by running NGD2VER with the -tf option already contains most of the code described previously (an illustration also follows) for defining and driving GTS.

Designs with No STARTUP Block

When the design lacks a STARTUP block, you can use the same test fixture file with little or no modification if you follow these guidelines in the following examples.

The following shows how you can drive the GTS signal in a Verilog-XL test fixture file at the beginning of a pre-NGDBuild Unified Library functional simulation. Spartan/XL, XC4000E/L/EX/XL/XV, or XC5200 designs containing no STARTUP block call the global tri-state net named “GTS.” Name the Verilog macro defining the global net “GTS_SIGNAL,” the name of the predefined macro used to model the global tri-state signal in the M1 Verilog Unified Library simulation models.

• Within the test fixture file, declare GTS as a Verilog register within the “test” module.
  
  module test;
  reg GTS;
  
  
• Set a macro called GTS_SIGNAL to test.GTS (the name of the global tri-state signal, qualified by the name of the test fixture module), using the `define compiler directive.
  
  

`define GTS_SIGNAL test.GTS;

GTS should be driven Low in an “initial” block.

   module test;

   reg GTS;
   `define GTS_SIGNAL test.GTS;

   initial
     begin

        GTS = 0;

In this example, deactivate the active High GTS signal by driving it Low, activating the outputs of the design.

Alternatively, you can reference the GTS_SIGNAL macro instead.

initial
begin
`GTS_SIGNAL = 0;

Designs With STARTUP block (Spartan/XL, XC4000E/L/EX/XL/XV, and XC5200 Devices Only)

Two differences exist when you assert global tri-state for a design specifying the STARTUP block and a design without a STARTUP block. First, for a connected GTS pin on the STARTUP block, the `define statement must set GTS_SIGNAL to the name of the net attached to the GTS pin on the STARTUP block.

`define GTS_SIGNAL net_connected_to_GTS_pin

Second, for a connected GTS pin on the STARTUP block, drive the external input port GSR_user_control_signal connected to the STARTUP block. This external input appears in your Verilog netlist as an input port. To tri-state your outputs, drive this signal High; to activate your outputs, drive it Low.

initial
begin
GTS_user_control_signal = 1;
#100 GTS_user_control_signal = 0;

In the following figure, the design contains a STARTUP block, and the GTS pin on STARTUP connects to an external input called mygts.

Figure 7.4 GST Pin in STARTUP Connected to External Input

Declare the external input “mygts” as a Verilog register and issue a `define directive setting GTS_SIGNAL to the name of the net connected to the GTS pin. You must issue this directive to connect the user logic to the global GTS model in the Unified Library simulation models for output buffers (such as OBUF and OBUFT).

   module test;
     reg mygts;

       `define GTS_SIGNAL test.uut.gts_in;
   .
   .
   .

   initial
     begin
        mygts = 1;  // if you wish to tri-state the
                    // device;
        #100 mygts = 0;     // deactivate GTS

For post-route timing simulation uses a procedure identical to that used for Unified Simulation.

For Unified Library functional simulation, define a wire called GTS, and set the GTS_SIGNAL macro to test.GTS. Toggle GTS_SIGNAL as shown.

   module test;
     wire GTS;
     `define GTS_SIGNAL test.GTS

   initial
     begin
      force `GTS_SIGNAL = 1;    // if you wish to 
                                  // tri-state the
                                  // device;
      #100 force `GTS_SIGNAL = 0; // deactivate GTS

For post-NGDBuild functional simulation, the actual net exists and must be further qualified by the design instance scope, “uut.”

   module test;
     // wire GTS;
     // `define GTS_SIGNAL test.GTS

     `define GTS_SIGNAL test.uut.GTS

   initial
     begin
       force `GTS_SIGNAL = 1;    // if you wish to 
                                  // tri-state the
                                  // device;
      #100 force `GTS_SIGNAL = 0;  // deactivate GTS

For post-route timing simulation, you can use the same test bench, unaltered.