You can use a constraints file to supply constraints information in a textual form rather than putting it on a schematic (a method sometimes more efficient than putting constraints on a schematic). An example of a constraints file follows, showing the user constraints file, calc_4ke.ucf, supplied with this tutorial. The constraints file syntax is the same for all device families. Because you only specified one pin location for one of the many inputs and outputs on the Calc schematic, you must use a constraints file to place the rest.
Instruct the place and route software to read and apply the .ucf file when the design reads into the Xilinx Design Manager. You can find this procedure in the “Using the Xilinx Design Manager” section.
# CALC_4KE.UCF
# User constraints file for CALC, XC4003E-PC84
# If the F pin is not constrained on the schematic,
# remove the comment (#) from NET F LOC=P50;
NET switch<7> LOC=P19 ;
NET switch<6> LOC=P20 ;
NET switch<5> LOC=P23 ;
NET switch<4> LOC=P24 ;
NET switch<3> LOC=P25 ;
NET switch<2> LOC=P26 ;
NET switch<1> LOC=P27 ;
NET switch<0> LOC=P28 ;
NET a LOC=P49 ;
NET b LOC=P48 ;
NET c LOC=P47 ;
NET d LOC=P46 ;
NET e LOC=P45 ;
# NET f LOC=P50 ;
NET g LOC=P51 ;
NET ofl LOC=P41 ;
NET gauge<3> LOC=P61 ;
NET gauge<2> LOC=P62 ;
NET gauge<1> LOC=P65 ;
NET gauge<0> LOC=P66 ;
NET stackled<3> LOC=P57 ;
NET stackled<2> LOC=P58 ;
NET stackled<1> LOC=P59 ;
NET stackled<0> LOC=P60 ;
# Remove the NOTGBLRESET line if STARTUP
# is not used in the schematic
NET notgblreset LOC=P56;