Using the Xilinx Design Manager

The Xilinx Design Manager is a graphic design flow and project manager. The Xilinx Design Manager takes your design, represented by the EDIF file from CONCEPT2XIL, and implements it in an FPGA or CPLD. You can also use the Xilinx Design Manager to generate timing information that you can import into Verilog-XL.

This section gives a brief overview of the design implementation flow. For a more in-depth discussion of the flow, including advanced implementation options, see the Development System Reference Guide.

1. At the UNIX prompt, within the xilinx.run directory, enter the following command.
   
   dsgnmgr &
   
   
2. Go to File New Project..., and click on Browse to find your Input Design. Select the calc.edf file. Click on OK.
   
   

   Figure 9.45 Xilinx Design Manager

   Each project has associated with it objects known as “versions” and “revisions.” Versions represent logic changes in a design (for example, adding a new block of logic, replacing an AND gate with an OR gate, or adding a flip-flop). Revisions represent different executions of the design flow on a single design version, usually with new implementation options (for example, higher place and route effort, a change in part type, or experimentation with new bitstream options). In the following steps, you make a new version and revision on which you run the implementation design flow.
   
   
3. In the Xilinx Design Manager, select Utilities Template Manager. Select New..., and give a name such as “calc.” Select the Implementation Templates button. Select Customize in the Template Manager, and in the Program Name field, enter NGD2VER. In the Program Options field, enter -ul. The ul option causes a `uselib directive to write out in the output .v file, needed in simulation.
   
   
4. Exit the Template Manager by clicking the Set button, then the OK button, and finally the Close button.
   
   
5. Within the Xilinx Design Manager, select Design Implement, which gives you the Implement dialog box, with fields for part type, design version, and revision as shown in the following figure.
   
   

   Figure 9.46 Implementation Dialog Box

6. If you chose not to use the CONFIG symbol in the earlier section, you need to specify the part type manually.
   
   Click the Select button to display a pull-down listing of available devices. Choose a Family of XC4000E, a Device of XC4003E, a Package of PC84, and a Speed Grade of -4. Click OK. The part number inserts into the Part field in the Implement dialog box.
   
   
7. Click on Options. The Options dialog box appears.
   
   

   Figure 9.47 Options Dialog Box

8. Click Browse by the User Constraints field. Select the calc_4ke.ucf file from the design directory, then Click OK.
   
   
9. Under Program Option Templates, select “calc” from the pulldown menu for Implementation. This causes the use of the “calc” template options in addition to the options selected in the GUI.
   
   
10. Under Optional Targets, ensure the selection of the following.
    
    
    • Produce Timing Simulation Data - generates a back-annotated Verilog netlist you can import into the Cadence tools.
      
      
    • Produce Configuration Data - generates a programming bitstream suitable for downloading into the Xilinx device.
      
      
    • Produce Post Layout Timing Report - generates a timing report file based on how the design actually routs.
      
      You can also select the following option.
      
      
    • Produce Logic Level Timing Report - generates a preliminary (pre-place and route) timing report based on the number of logic levels in each signal path. Because this report generates before the place-and-route layout step, it does not contain information on device routing. Look at this report before place and route to see how much “routing slack” exists in a design.
      
      
11. Under Program Option Templates Implementation, select Edit Template. The XC4000 Implementation Options dialog box appears.
    
    
12. Select the Interface tab. In the Interface pane, look under Simulation Data Options and verify that Format is set to Verilog and that Correlate Simulation Data to Input Design is selected.
    
    
13. If you used LogiBLOX components in the design, set the Macro Search Path in the Translate Options box to the directory which contains the LogiBLOX module file, name.ngo. In this case, if you created the addsub4 module earlier in the tutorial, point the Macro Search Path to the directory where addsub4.ngo resides, generally the calc project directory.
    
    
14. Click OK to return to the Options window. Click OK to return to the Implementation dialog box.
    
    
15. Verify “ver1” as the version and “rev1”as the revision, then click Run. The Flow Engine starts as shown in the next figure.
    
    

    Figure 9.48 The Xilinx Flow Engine

    The status bar shows the progress of the implementation flow with the following stages.
    
    
    • Translate - converts the design EDIF file into an NGD file
      
      
    • Map - groups basic elements (“bels”) such as flip-flops and gates into logic blocks (“comps”); also optionally generates a logic-level timing report
      
      
    • Place & Route - places comps into the device, and routes signals between them
      
      
    • Timing - generates timing simulation data and an optional post-layout timing report
      
      
    • Configure - generates a bitstream suitable for downloading into and configuring a device
      
      
16. When the implementation completes, an Implementation Status box appears with the following message.
    
    

      Implementing revision ver1->rev1 completed successfully.

Click on View Logfile to display the logfile from Flow Engine. The report displays in vi. To exit the viewer, type :q! and press Return. Click OK in the Implementation Status dialog to return to the Xilinx Design Manager.

NOTE

To use another text editor, such as Emacs, as the report viewer, select File Preferences from the Xilinx Design Manager.