After verifying the functional correctness of your design, use CONCEPT2XIL to translate your Concept design into a Xilinx-ready EDIF netlist. Run CONCEPT2XIL always as the first step in implementing a design. Whenever you make changes to your schematic, you must run CONCEPT2XIL again so that the Xilinx software can process those changes.
The command line for using CONCEPT2XIL follows.
concept2xil -family target_technology design_name
target_technology is xce4000e, xce4000x, xce3000, xce5200, or xce9000. This command line and the command line used for creating a functional simulation Verilog netlist are virtually identical, except for the lack of the -sim_only option. You do not have to use the -sim_only option for CONCEPT2XIL even if you plan to simulate; this option merely stops CONCEPT2XIL from creating a .edf file, improving execution performance.
CONCEPT2XIL puts its output in xilinx.run by default (you can use the -rundir option to change that), and uses the files cds.lib and global.cmd to find the proper libraries (use the -cdslib and -gcmd options to change). For the Calc design, enter the following command in the main design directory.
concept2xil -family xce4000e calc
Upon completion, CONCEPT2XIL creates an .edf file, along with the V and VF files needed for simulation (identical to those created earlier for functional simulation). CONCEPT2XIL also creates a log file called concept2xil.log in the design directory.
