See the “Introduction” chapter for the design flow when using the Cadence interface for describing the general steps for creating a design using the Cadence interface.
This tutorial uses an incremental design methodology. In incremental design, the design processes completely through the flow at least once, you make small changes to the design, and then you process the design again. Place and route information from the previous design processing cycle constrains subsequent cycles of the same design. When you use this method, timing information in a design remains relatively stable through many processing cycles. Also, place and route time usually decreases because much of the processing occurred in previous cycles.
The tutorial design can be targeted for an XC4000E or XC9500 device. You can use a Xilinx demonstration board to test the functionality of your design. Make sure your demonstration board and software support your selected device. To determine compatibility, refer to the release notes that came with your software package.
This tutorial uses the following conventions to refer to the various device families.
