You must have the following versions of software are to perform this tutorial.
Before beginning the tutorial, set up your workstation to use Cadence and Xilinx Development System software as follows.
When a schematic is saved in Concept, a directory is created in the project directory with the same name as the schematic. This directory contains body files, logic files, and HDL Direct generated Verilog text files. HDL Direct creates a structural Verilog netlist of the schematic sheet, which the Xilinx tool set requires for translation.
This tutorial uses file names and directory names in lower case and refers to the design example as Calc.
You complete the Calc design in this tutorial. Installing the tutorial creates the $XILINX/cadence/tutorial directory, design directories, and the tutorial files needed to complete the design are copied to the calc_sch directory. Some of the files you need to complete the tutorial design are not copied, because you create these files in the tutorial. However, solutions directories with all input and output files are provided. They reside in the $XILINX/cadence/tutorial directory and are listed in the following table.
| Directory | Description |
|---|---|
| calc_sch | Schematic (Concept) tutorial directory |
| calc_4ke | Schematic solution directory for XC4003E-PC84 |
| calc_9k | Schematic solution directory for XC95xxx-PC84 |
| calc_blx | Schematic solution directory using LogiBLOX |
The solution directories contain the design files for the completed tutorial, including schematics and the bitstream file. To conserve disk space, some intermediate files are not provided, except in the calc_4ke directory, which is complete. Different intermediate files are created for different device families. Do not overwrite any files in the solutions directories.
The calc_sch directory contains the incomplete copy of the tutorial design. The installation program copies a few intermediate files to the calc_sch tutorial directory, and you create the remaining files when you go through the tutorial. As described in a later step, you copy the calc_sch directory to another area and work through the tutorial in this new area. The next table lists and describes the directories and files in the calc_4ke solution directory.
| Directory or File Name | Description |
|---|---|
| calc | Top-level design directory |
| control | Design directory for control module |
| statmach | Design directory for state controller module |
| alu1 | Design directory for ALU1 module |
| alu_blox | LogiBLOX version of ALU1 design component |
| muxblk2 | Design component for arithmetic function in ALU1 |
| andblk2 | Design component for arithmetic function in ALU1 |
| orblk2 | Design component for arithmetic function in ALU1 |
| xorblk2 | Design component for arithmetic function in ALU1 |
| muxblk5 | Design component for multiplexer arithmetic outputs in ALU1 |
| muxlbk2a | Design component for multiplexer operator function in control |
| stack | Design component for stack |
| seg7dec | Design component for 7-segment decoder |
| debounce | Design component for debounce circuit |
| osc_3k | Design component interface to RC circuit on demonstration boards; generates clock |
| xilinx.run | Default run directory for CONCEPT2XIL |
| calcf.stim | Test fixture for use in Verilog-XL simulation |
| calc.edf | EDIF netlist files created by CONCEPT2XIL |
| concept2xil .log | CONCEPT2XIL log file |
| calc.ngo | Native Generic Object created by EDIF2NGD |
| calc_4ke.ucf | User Constraints File |
| calc.ngd | Native Generic Design created by NGDBuild |
| calc.mrp | Mapping report created by MAP |
| calc.pcf | Physical Constraints File created by MAP |
| calc.ncd | Native Circuit Description created by MAP |
| calc_r.ncd | Routed NCD file created by PAR |
| calc_r.twr | Timing report created by Trace (TRCE) |
| time_sim.v | Structural Verilog netlist of Calc for simulation |
| time_sim.sdf | Standard Delay Format file for timing simulation |
This manual uses the terms “testbench” and “test fixture” synonymously.
