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Making Incremental Design Changes

After initially placing and routing a design, you often must go back to the schematic and make slight modifications to the original design. When this situation occurs, you can “recycle” much of the place and route information from the previous design iteration, as much of it does not change. This process, known as incremental design, uses the NCD file (containing partition, placement, and routing information) from the prior place and route run as a guide.

Because much of the place and route information extracts from the guide file, incremental design greatly reduces the place and route time. The reuse of place and route information also results in more stable timing over a number of guided place and route iterations. After a section of your design passes your timing requirements, incremental design ensures that it passes in the future, even if you modify other parts of the design.

In this section of the tutorial, you make a small change to the schematic and reprocess the design using the guide options available in the Xilinx Flow Engine.

NOTE

Consider a small design change the addition, removal, or replacement of only a small amount of logic in the design; the exact amount depends on the size of the design. If you make radical changes to a design, especially to existing portions of the design, guiding the design can produce incompatible results.

Making an Incremental Schematic Change

Make a simple, yet immediately visible on the demonstration board, change to the Calc schematic. For example, assume you no longer need the reset opcode and must remove it form the design. Do so by grounding the `R' pins that serve as inputs to the FDRE and FD4RE macros in the ALU1 schematic. The MAP program automatically optimizes the logic that generated the original reset signal, and the logic it drove, out of the netlist.

Open Concept and load the Calc schematic.

  1. Open the ALU1 schematic (edit alu1).

  2. Zoom in on the lower right quadrant of the schematic.

  3. Enter into Delete mode.

  4. Delete the AND5B2 component that generates the GRESET net feeding the FDRE and FD4RE. Delete the leftover dangling nets, also.

  5. Connect a ground symbol to the dangling QRESET net. Find the GND symbol in the Add Part xce4000e of the Xilinx Library menu. See the following figure.

  6. Write the schematic.

  7. Exit Concept, and retranslate using CONCEPT2XIL.

Figure 9.49 Grounding the Reset Logic

Translating the Incremental Design

Translate the guided Calc design by turning on the guide options in Flow Engine. The following instructions demonstrate an alternative method of running Flow Engine that offers more control over the implementation flow.

  1. In the Xilinx Design Manager, select calc, then choose Design New Version.

  2. The New Version dialog box appears with the Name field automatically filled in as “ver2.” You can also add a comment to the new version. This comment appears in the project view next to the version number. Click OK.

    NOTE

    You can add a comment to any version or revision in the project view by selecting that version or revision, then selecting Right Mouse Button Properties.

  3. Select the newly created “ver2” in the project view, then select Design New Revision.

  4. The New Revision dialog box appears with the Name field automatically filled in as “rev1” and the Part field automatically filled in as “XC4003E-4-PC84.” You can add a comment to the new revision. Click OK.

  5. Select the newly created “rev1” in the project view, then select Tools Flow Engine. Alternatively, you can click the Flow Engine icon in the Toolbox.

  6. The Flow Engine appears. However, unlike the procedure you used in the first revision, the implementation flow does not start automatically. This allows you to step forward and even backward through the implementation flow by individual stages, using the audio-player-like buttons at the bottom of the Flow Engine window, or the selections underneath the Flow menu.

    Select Setup Options from the menu bar. The Options dialog box appears as before.

  7. Go through the different options as before and verify that the settings you gave in the previous revision carried over into this revision.

  8. In the Guide Design field, select Last. This sets the previous revision of the placed and routed design. In this case, it has the same effect as selecting ver1 rev1.

  9. Click OK to return to Flow Engine.

  10. Run the implementation as before by clicking the “play” button (on the far left) at the bottom on the Flow Engine window.

  11. When all steps complete successfully, select Flow Close to exit Flow Engine.

Verifying the Change in the Demonstration Board

Verify that the change implemented by downloading the new bitstream to the demonstration board, as you did previously. As before, see the “CALC Tutorial” chapter of the Hardware Debugger Reference/User Guide for more information. Before running through this tutorial, ensure the selection of the ver2 rev1 revision in the project view.

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