Refer to the “Glossary” appendix for definitions of HDL Direct and SCALD.
The M1 release of Xilinx tools does not support SCALD methodology when entering designs. Therefore, use the HDL Direct library component counterparts in place of any “standard” library components whenever one exists. Furthermore, you must enable HDL Direct whenever you save a schematic sheet. Put the following commands in your startup.concept file to activate HDL Direct every time you invoke Concept.
set hdl_direct on
set hdl_checks on
set check_signames on
set check_net_names_hdl_ok on
set check_port_names_hdl_ok on
set check_symbol_names_hdl_ok on
set capslock_off
runopl installation_path_to_cadence/tools/fet/concept/hdl_direct/bin/autosym
When processing designs entered using SCALD methodology, refer to the Concept User Guide (from Cadence) for guidelines on converting these designs for HDL Direct compliance.
This release does not support the SIZE property. Use iterated instances instead (which essentially consists of adding a bus index to the PATH attribute of the symbol body instance). Refer to the Cadence HDL Direct User Guide for more information on iterated instances.
