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Completing the Calc Design

To complete the tutorial design, you need to add a few design objects to the Calc schematic using Concept.

If you need to stop the tutorial at any time, save the work you have done by first selecting File Write from the Command Menu. A window appears that reports the results of HDL Direct. After reviewing the contents of this window, press Return inside that window to close it. If it reports errors, you can ignore them and write it out anyway.

Design Description

The top-level schematic of the Calc tutorial design already exists. Each of the blocks in the schematic, such as CONTROL or ALU1, links to a second-level module that describes its logic. Additionally, any second-level module can contain another block that references a third-level drawing, and so on. This organization is known as a hierarchical structure.

In this tutorial, you add three symbols to the ALU1 block schematic to complete it. First, you create the ANDBLK2 and ORBLK2 symbols and their underlying schematics and then add them to the schematic. Additionally, you add the FD4RE symbol from the Unified Libraries to the ALU1 block. After finishing the ALU1 block, you add the STARTUP block to the top-level Calc schematic to tie the device's global reset network to a device pin. To complete design entry, you add a CONFIG block, which lists a set of instructions that dictate how the implementation tools should process the design.

The Calc design is a four-bit processor with a stack. The processor performs functions between an internal register and either the top of the stack or data input from external switches. A register stores the results of the various operations and results display in hexadecimal on a seven-segment display. The top value in the stack displays in binary on a bar LED. A count of the items in the stack displays as a “gauge” on another bar LED.

The design consists of the following functional blocks.

Before proceeding, close (quit) the Calc schematic window. If a dialog box appears asking if you want to save any changes, choose NO.

Targeting XC9500 Devices

To target an XC9500 part, you can proceed with this tutorial (even though it is set up for a 4000E part). A discussion later in this tutorial describes what you need to convert the design for an XC9500 instead of the XC4000E.

Creating Schematics for ANDBLK2 Symbol

You need to create schematics and symbols for ANDBLK2 and ORBLK2. You can then reference the schematics in a higher-level schematic by instantiating the corresponding symbol bodies.

Opening a Schematic

To open a new schematic sheet for ANDBLK2, type “edit andblk2” in the Message Window.

Adding the First Component to a Schematic

  1. From the Command Menu, select Add Part. The Component Browser appears. See the following figure.

    Figure 9.5 Component Browser Menu

  2. Select components from the correct library for the target device (xce4000e for this tutorial). The Component Browser defines several libraries. To select the library with the components you want to add, use the left mouse button on the Component Browser button next to “Library:” (currently showing “calc.wrk”) as seen in the “Placing a Component” figure. Select the xce4000e library.

  3. Scroll down and select AND2.

  4. The outline of a 2-input AND gate appears in the schematic window.

  5. Move the symbol outline roughly to the center of the schematic entry window and click the left mouse button to place the object.

Figure 9.6 Placing a Component

Placing Additional Components

To select another component of the same type, click the middle mouse button (while still in Add Part mode) anywhere in the schematic window. Then position the component and use the left button to place it on the sheet. Using this method, select and place a second AND2 symbol.

Copying a Component

Use the Copy command to add more components by copying a component that already appears on the schematic.

  1. Select the Select command in the Command Menu with the left mouse button.

  2. Move the mouse above and to the left of the two symbols on the sheet, and click the left mouse button.

  3. Move the mouse below and to the right of the two symbols. A white box appears surrounding the two symbols.

  4. Click the mouse button again to select the objects inside the box. All selected items highlight. Note that if you zoom or pan across your schematic at this point, all selected components deselect.

  5. Select the Copy command in the Command Menu.

  6. Click the middle mouse button to copy the entire highlighted group (left mouse button only copies the nearest component, and not the entire group). Place the two copied gates above the original two and click the left mouse button. If necessary, use the right mouse button to pan across the schematic (hold it down while moving mouse).

  7. Press F2 to view the entire schematic (or use stroke “W”). The schematic now looks like the following figure.

Figure 9.7 Component Placements for ANDBLK2

Moving a Component

If you make a mistake when placing a component, you can use the menu commands to move the component.

  1. Select the Move command in the Command Window, and click on the component with the left mouse button.

  2. Move the component to the desired location, and again click the left mouse button.

Adding and Labeling Buses in a Schematic

For convenience, you can draw a set of signals as a bus rather than as several separate wires.You do not have to physically connect a bus to the nets that make up the bus. Several schematics in the Calc design have short bus segments that do not connect to anything in order to establish pin connectivity to a bus pin on the symbol corresponding to the schematic. A bus must exist on the schematic if you want to use a bus pin to represent a set of signals.

Concept places a bus on the schematic as a wire. When a label with a bus index attaches to the wire, Concept automatically changes the wire to a bus (redrawing it as a heavier line).

Add buses to the schematic as follows.

  1. Select Wire from the Command Menu, or enter “wire” in the Message Window.

  2. Draw a wire by clicking the left mouse button to specify the starting point, moving the mouse to a new position, then clicking the button again to make a bend in the wire or to connect it to a pin. Terminate the wire by clicking the mouse button in the same place twice. Add the three buses shown in the “ANDBLK2 Schematic with Buses” figure (add wires where you see a bus in the figure; they convert to buses in the next step). You can zoom the schematic view out before adding the buses.

  3. If you make a mistake, select Delete in the Command Menu and click on the wire you want to remove.

  4. After adding the three buses, select Signame in the Command Menu.

  5. Click on the left-most wire (labeled A<3..0> in the figure). A small red box appears next to the wire. In the Message Window, type “A<3..0>” and press Return to label the bus.

  6. Use a procedure similar to the previous step to label the other wires “B<3..0>” and “Q<3..0>.”

Figure 9.8 ANDBLK2 Schematic with Buses

Adding Wires and SLICEs to a Schematic

You must add wires to attach the appropriate pins on the gates to the buses. You can enlarge the view of the components to make it easier to draw the nets.

In order to connect a wire to a bus, add a SLICE from the hdl_direct_lib. The SLICE can connect a bus to a wire.

  1. Select Add Part in the Command Menu. The Component Browser appears.

  2. Click the left mouse button on the button to the right of “Library:” in the Component Browser. Select hdl_direct_lib. Scroll down the menu to select SLICE with the left mouse button.

    NOTE

    Do not use the TAP from the older SCALD standard library; HDL Direct compliance requires that you use the appropriate corresponding hdl_direct components in place of SCALD components wherever applicable.

  3. Move the cursor into the schematic window and click the middle mouse button to rotate the SLICE symbol. Click the mouse until the SLICE achieves the orientation shown in the “Placing SLICEs” figure (for the A<3..0> bus). Then, place the SLICE so the left diagonal side touches the bus, and the right horizontal side aligns with one of the AND2 pins. Click the left mouse button to place.

    NOTE

    You do not have to place the SLICE in any particular orientation, except that the diagonal portion should connect to the bus.

    Click the left or middle mouse button after placing the SLICE to select a new SLICE. Note this is a copy of the previous SLICE, so there is no need to rotate it. Place this SLICE below the previous SLICE, so it aligns with the next AND2's top pin.

    Figure 9.9 Placing SLICEs

  4. Place the remaining 2 SLICEs for the A<3..0> bus, and add 4 SLICEs for the B<3..0> bus and Q<3..0> bus. You can perform this step either by continuing to click the left or middle mouse button (assuming you have not left Add Part mode), or by selecting SLICE each time in the Component Browser. Alternatively, type “add slice” in the Message window.

    The “ANDBLK2 with All Wires and Buses Connected” figure shows a different orientation for the Q<3..0> SLICE. Simply click the middle mouse button until you get this orientation.

    If you make a mistake, you can select either Delete or Move.

  5. Select “wire” from the Command Menu or enter “wire” in the message window.

  6. Move the cursor to the top input pin of the top AND2 gate, then click the left mouse button.

  7. Move the cursor to the left of the SLICE at the top of the left-most bus so that the wire connects to the output of the SLICE. Click the left mouse button to terminate the wire.

  8. Add the remaining nets as shown in the following figure.

Figure 9.10 ANDBLK2 with All Wires and Buses Connected

Adding Values to SLICE Symbols

At this point, you labeled all buses in the ANDBLK2 schematic. However, for the nets ripped off the bus via the SLICE symbol, you must attach an attribute to the SLICE to indicate which bit of the bus the net represents. You need to change the current default value of “?” to a number within the bus bounds.

You can change these values by individually changing the BN attribute on each SLICE, or by using the “bustap” command to change this attribute on a set of SLICEs, all at once.To change each value individually, use the following procedure.

  1. Select Change in the Command Menu. Use the left mouse button to select the top SLICE of A<3..0>. The “?” (default undefined BN value) turns red, and a cursor appears beside it. Press the right cursor followed by the BackSpace key to delete the current value, and type “0” followed by Return. The SLICE now appears as in the figure below. If you accidently select any elements besides the SLICE you want to edit, select the “;” key in the command menu and reselect Change.



    Figure 9.11 Adding an Attribute to a SLICE

  2. Repeat this procedure for all SLICEs for the A<3..0> bus only. Label from top to bottom, with “0” on top and going sequentially to “3” on the bottom. Refer to the “Using the Bustap Command” figure.

    The label sizes increase as shown in the “Using the Bustap Command” figure.

  3. Although you can use the same procedure to add values to the SLICEs of the other two buses, you can alternatively use another command called “bustap.” Type “bustap 0 3” in the Message Window.



    Figure 9.12 Using the Bustap Command

  4. Position the mouse cursor above the first “?” on the top SLICE of the B<3..0> bus and click the middle mouse button. Position the mouse below the last “?” on the bottom SLICE of the B<3..0> bus, as shown in the previous figure.

  5. Click the middle mouse button again. All the “?” change to numbers, beginning from 0 and going to 3.

  6. Use either Change or bustap to modify the SLICEs on the Q<3..0> bus.

Adding Ports

Add port symbols to nets and buses to define the connectivity between a schematic and its associated symbol. For the ANDBLK2 schematic, all three buses need ports. Input signals get INPORTs and output signals get OUTPORTs.

Add ports to the schematic as follows.

  1. Select Add Part mode from the Command Menu, and select the hdl_direct_lib library in the Component Browser.

  2. Scroll down to select the INPORT symbol.

  3. Position the INPORT so that the symbol pin's right side touches the A<3..0> bus's left end. Click the left mouse button to place.

  4. Place another INPORT at the end of the B<3..0> input bus, on the left side of the window.

  5. Next select an OUTPORT symbol from the library and place it at the end of the output bus. Instead of selecting it from the Component Browser, try typing “add outport” in the Message Window.

  6. Press F2 to view the entire schematic. The schematic appears as in the following figure.

Figure 9.13 Adding Ports

Saving the Schematic

The schematic is now complete. Check and save the schematic as follows.

  1. Select File Write in the Command Menu. If an errors occur, recheck the schematic against the figure below. You can use the command “error” to have Concept show on the schematic itself errors that exist in the drawing. After Concept finishes checking the schematic, it automatically calls HDL Direct to write out the Verilog netlist. A separate Xterm window opens, and this check must complete successfully also. If completion does not succeed, you must correct the schematic (the Concept command “error” does not point out errors found in the HDL Direct window).



    Figure 9.14 Completed ANDBLK2 Schematic

  2. After correcting all schematic errors, write the design again if necessary.

Figure 9.15 Successful Write with HDL Direct

Creating Schematics for ORBLK2 Symbol

The ORBLK2 schematic resembles the ANDBLK2 schematic. To create schematics for the ORBLK2 symbol, you can use the ANDBLK2 schematic and simply replace the four AND2 gates with OR2 gates.

  1. Press the F2 key to unselect everything on the ANDBLK2 schematic and to view the entire schematic.

  2. Enter in the Message Window the command “replace or2.” This replaces any selected component selected with the OR2 symbol.

  3. Click on the four AND2 gates with the left mouse button to convert them to OR2 gates.

  4. Enter the command “write orblk2” in the Message Window. This saves the schematic under the new name “orblk2.”

Figure 9.16 Completed ORBLK2 Schematic

Creating the ANDBLK2 Symbol

The following subsections explain how to create the ANDBLK2 symbol.

Creating the Symbol Outline

  1. Enter the command “edit andblk2.body” in the Message Window. Previously, when you typed in the command “edit,” you did this to create or modify a schematic. Typing “edit component_name” means “edit component_name.logic.” The “logic” extension references the schematic, whereas the “body” extension references the symbol.

  2. A blank grid appears with the name of the symbol and an origin “X” in the center. You can now begin to draw the symbol's body with the “wire” command. Select “wire” in the Command Menu.

  3. Draw an enclosed shape (usually a rectangle) around the origin. Make it large enough to have two inputs on the left side and one output on the right side.

  4. Add wire stubs to represent the symbol pins. Make each pin a wire segment that begins on the outline of the main body but points away from the body. Make each pin begin and end on a grid point. For the andblk2 symbol, place the two input pins on the left and one output pin on the right, for a total of three pins.

  5. Enter the command “dot” in the Message Window. Position the mouse over the dangling end of a pin, and click to place the dot. Place a dot at the end of all other pins.

  6. Select the command “signame.” Click on the upper left dot and type in the string “A<3..0>” to make it appear on the drawing. The name of the pin must exactly match the name of the signal connected to the INPORT or OUTPORT symbol. Do the same for the lower left pin (B<3..0>) and the right pin (Q<3..0>).

Adding Text

  1. Adding signal names (signames) to the pins correlates the pins to the underlying schematic, but you cannot see these signames on the symbol when you use it. To add a visible label to the pin, use the command “note.” After entering this command, type in the string “A<3..0>” and position it near the top left pin, inside the symbol.

  2. If you consider the text too large, type in the command “set size 0.5” to halve the size of the text. This does not reduce the size of existing text. To replace the existing text with smaller text, you must delete it and re-enter it with the “note” command after you enter “set size 0.5.”

  3. Place the text “B<3..0>” and “Q<3..0>” by their respective pins. Also add the name of the symbol ANDBLK2 to the body drawing by attaching it to the body as another NOTE at the top of the symbol.



    Figure 9.17 Completed ANDBLK2 Symbol

  4. When the drawing meets your expectations, do a “write.”

  5. To return to the normal text size, enter “set size 1.”

Creating the ORBLK2 Symbol

Create the symbol for ORBLK2, as shown in the “Adding ANDBLK2 and ORBLK2 to ALU Schematic” figure. Because ORBLK2 resembles ANDBLK2, use the ANDBLK2 symbol and modify the text.

  1. Select the Change mode. Select the text ANDBLK2, and convert it to ORBLK2. You do not need to make other modifications.

  2. Enter in the command “write orblk2.body.” This command causes Concept to save the modified schematic under the new name.

Editing the ALU1 Schematic

By now you created symbols for ANDBLK2 and ORBLK2. You also created underlying schematics for these symbols. Next, place the symbols in the ALU1 block schematic.

  1. Enter “edit calc” in the Message Window (the same as “edit calc.logic”).

  2. If you left the Component Browser running, select the calc.wrk library and click with the left mouse button on the ALU1 component. Select the logic view (ALU.LOGIC.1.1). The ALU1 schematic appears. If you previously closed the Component Browser, you must type “edit” once to start it.

NOTE

You can enter “edit alu1” instead (replacing both step 1 and step 2), but entering “edit” allows you to use the mouse to descend hierarchy when in the “edit” mode. This only works when the Component Browser runs, otherwise, you must type “edit” once to start the Component Browser.

Placing User-Created Components

Place the ANDBLK2 and ORBLK2 symbols on the schematic as shown in the “Adding ANDBLK2 and ORBLK2 to ALU Schematic” figure. Use the same procedure used to place the AND2 gate from the Xilinx libraries when you created the ANDBLK2 schematic.

  1. Use the Zoom button to zoom into the empty area near the center of the schematic, between the XORBLK2 and ADSU4 symbols.

  2. Select Add Part. From the Component Browser, select the calc.wrk library, and scroll down to choose the ANDBLK2 component. All user-created components come from the design.wrk library (or whatever file you referenced in the “use” line in the global.cmd file). Alternatively, enter “add andblk2” in the Message Window.

  3. Move the cursor to the correct location as shown in the next figure.



    Figure 9.18 Adding ANDBLK2 and ORBLK2 to ALU Schematic

  4. Press the left mouse button to place the component.

  5. Follow the same procedure to add the ORBLK2 symbol. Refer to the ALU1 schematic in the preceding figure for proper placement. If you make a mistake when placing a component, enter Move mode and select the component to move it.

Now you add the FD4RE and AND5B2 components to the ALU1 schematic. Find the FD4RE component in the xce4000e Xilinx Unified Libraries; it consists of four flip-flops with a clock enable. The AND5B2 component is a five-input AND gate with two inputs inverted (or “bubbled,” hence the “b” in the component name).

NOTE

You can find these components in all libraries, including those for the XC4000E and XC9500 devices.

  1. Use F2 to display the entire ALU1 schematic. Use the Zoom button to zoom into the open area in the lower right-hand corner.

  2. Select Add Part from the Command Window.

  3. Select the appropriate family library (xce4000e or xce9000) in the Component Browser.

  4. Choose FD4RE from the menu. Move the cursor into the schematic window; an outline of the FD4RE component appears.

  5. Move the component to lower right corner of the schematic, approximately to the location shown in the figure below.

  6. Press the left mouse button to place the component.

  7. Repeat steps 4 through 6 to place the AND5B2 component next to the FD4RE as shown in the “Adding FD4RE and AND5B2 to ALU Schematic” figure. You can instead use the command “add and5b2.”

Figure 9.19 Adding FD4RE and AND5B2 to ALU Schematic

Adding Nets, Buses, Ports and Labels

Use the instructions in the following sections to add nets, buses, ports and labels to Calc.

FD4CE and AND5B2

Next complete the addition of the FD4RE and AND5B2 symbols by adding nets, buses, and labels using the following steps.

  1. Add the necessary nets and buses to complete connections for FD4RE and AND5B2 as you did for the previous schematic. The following figure displays the labeled nets and buses for FD4RE and AND5B2.

  2. Add ports to the nets and buses attached to the FD4RE and AND5B2, as shown in the “Nets, Buses, and Ports for FD4RE and AND5B2” figure. Attach INPORTs to nets and buses corresponding to ALU1 inputs, and OUTPORTs to ALU1 outputs.

    NOTE

    Always use the IPAD/OPAD symbols for your external FPGA/CPLD ports. The symbols INPORT and OUTPORT are used for connections to different levels of hierarchy in your design.

  3. To add net names to nets, use Signame in the Command Window and type in the name of the signal. This replaces the red box over the net with your net name after you press Return.

Figure 9.20 Nets, Buses, and Ports for FD4RE and AND5B2

WARNING

Whenever you take an existing schematic and add or remove INPORTs or OUTPORTs, or IPADs or OPADs, HDL Direct reports the following message.

   Error #168: Schematic has port but port does not exist in the entity declaration. The entity declaration may need to be updated.
   Port name: <port_name>
   Entity file location: <entity_location>
   First object description:
    Page: <page_#> Instance: <instance_name> 
    Cell name: <IN_or_OUTPORT>
   Second object description: 
    The entity declaration for <schematic_name>.
    
    Concept HDL Direct: Done.
   Would you like to overwrite the entity declaration 
   <design_name>/<sub-hierarchy>/entity/vhdl.vhd
   with a new entity declaration derived from this schematic? [y/n]

Answer “y” to this query; it is not an actual error. To ensure no errors, do another “write.”

ANDBLK2 and ORBLK2

Next, complete the addition of ANDBLK2 and ORBLK2 to the ALU1 schematic.

  1. Add the necessary buses to complete connections to ANDBLK2 and ORBLK2. The “Nets, Buses and Labels for ANDBLK2 and ORBLK2” figure displays the labeled nets and buses for ANDBLK2 and ORBLK2.

  2. Use the following figure to name the added buses by using the same Signame command from the previous section. You only need to label the output buses of the two components because the inputs to these components connect to pre-labeled buses.

Figure 9.21 Nets, Buses and Labels for ANDBLK2 and ORBLK2

Adding Labels to Components

Add labels to components. Error and warning messages often reference component labels, and labels also appear in simulation netlists. Also, net names at lower levels of hierarchy are referenced using the following format.

   ...component_label/component_label/net_label

In the ALU1 schematic, labels already exist for the MUXBLK2, XORBLK2, and MUXBLK5 blocks.

To add a label to the ORBLK2 instance, follow these steps.

  1. Press the Attributes button in the Command Menu.

  2. Use the left mouse button to select the ORBLK2 symbol. The next figure shows the dialog box that appears.



    Figure 9.22 Attribute Form

  3. In the field under Value and to the right of Path, replace the “?” value (or whatever string appears in this field) with the value “ORBLK2.”

  4. Select Done to close the Attribute Form.

  5. You can use the Move command to position the text as shown in the following figure. Click the left mouse button to select and to place the text.

  6. Label the ANDBLK2 symbol the same way using the label ANDBLK2, as shown in the “Adding Component Labels to ALU1 Schematic” figure.

  7. Give the FD4RE component the label ALUVAL.

Figure 9.23 Adding Component Labels to ALU1 Schematic

The completed ALU1 schematic appears in the following figure.

Figure 9.24 Completed ALU1 Schematic

Saving the ALU1 Schematic

Write the schematic. If errors occur, resolve them and then write the schematic again.

Exploring Xilinx Library Elements

The Xilinx libraries contain three types of elements.

Only the XC4000 family library currently provides RPMs.

Place all three types of library elements on a schematic in exactly the same way.

Viewing a Xilinx Soft Macro Schematic

Soft macro schematics include schematics such as those you make for your own designs. You can load one of these schematics and use the “write new_filename” command to save it under another name, and then edit this new schematic to customize it to your needs.

Open the schematic underneath the FD4RE symbol as follows.

  1. Enter the command “edit.” You need to type it again if the Component Browser was previously closed (not reduced to an icon).

  2. Select FD4RE with the left mouse button. As shown in the following figure, FD4RE consists of four fdre symbols.

  3. Enter “ret” to return to the previous schematic.

Figure 9.25 FD4RE Schematic from XC4000E Library

Viewing a Xilinx RPM (XC4000E Family Only)

NOTE

The following description of RPMs contains detailed information about the XC4000E architecture. Refer to The Programmable Logic Data Book for more information on the XC4000E CLB structure and fast carry logic.

If your design does not target the XC4000E family, read this section, but do not perform any of the commands. Continue the tutorial with the “Opening the Calc Schematic” section.

The ALU1 contains a component from the Xilinx library, ADSU4, a four-bit wide adder/subtracter. If your design targets the XC4000E library, this schematic implements as a Relationally Placed Macro (RPM). If your design does not target the XC4000E library, ADSU4 implements without this placement information.

Like schematic of soft macros, RPM schematics are schematics such as you make for your own designs. To modify an existing Xilinx RPM schematic, save the schematic and associated symbol to a different name, then edit this new schematic to customize it to your needs.

Elements placed in the ADSU4 RPM schematic include CY4 components and FMAPs. The CY4 symbol gives you the ability to specify fast carry logic functionality from the schematic. Fast carry logic, a hardware feature in XC4000E parts, allows very fast arithmetic-type functions.

The FMAPs map logic functions to function generators in configurable logic blocks (CLBs), arranged in a rectangular grid in the die. Both the CY4 symbols and FMAP symbols in ADSU4 have RLOC attributes. RLOCs attach to the symbols that assign relative locations to the CLBs. Although you can use carry symbols as well as FMAPs and other mapping components in your own schematics, Xilinx Library RPMs do not require knowledge of them. Do not casually attempt to create macros containing carry logic and FMAPs. For a description of these components, see the Xilinx Libraries Guide.

Push into the ADSU4 schematic as follows.

  1. Enter “edit adsu4” (or “edit” and use the mouse).

  2. Use the Zoom button (or stroke “Z”) to zoom into the upper portion of the schematic as shown in the “Upper Portion of the ADSU4 RPM Schematic” figure.

  3. Select the Attribute button.

  4. Select the FMAP component in the upper right corner.



    Figure 9.26 Upper Portion of the ADSU4 RPM Schematic

  5. The Attribute Form window appears displaying the attributes on the symbol, as shown in the preceding figure. The RLOC attribute, set to R0C0.G, indicates that this function maps to the G function generator of the upper-left corner (row zero, column zero) CLB in the RPM. RPM origins reference the upper left-hand corner of the macro. You can also call up the Attribute Form with the stroke that resembles a lowercase cursive “a.”

  6. Close the window to return to the ADSU4 schematic window.

  7. Hold down the right mouse button (or use the arrow keys) to pan around the schematic and look at the RLOCs. Note that logic maps to three CLBs, designated as R0C0, R1C0, and R2C0. Therefore, this RPM uses three CLBs arranged in a column. You can find information on the number of CLBs used and the shape of the logic block for each RPM in the Xilinx Libraries Guide. These locations are relative, not absolute. There are no constraints to placing the macro in the uppermost CLB in the left-most column. Regardless of the RPM's absolute location, the logic associated with the FMAP with the location R0C0 is always at the top, the R1C1 CLB directly follows, and so on.

  8. Close the ADSU4 schematic and return to the ALU1 schematic, using the “ret” command.

Opening the Calc Schematic

Close all open schematic or symbol windows except for the top-level Calc schematic window. If you closed the Calc window, open it. The Calc schematic appears on the screen.

Using the XC4000E Oscillator

If your design does not target the XC4000E family, read this section, but do not perform any of the commands.

The XC4000E family devices contain an on-chip clock generator, which makes it unnecessary to use an external circuit for this purpose. The imprecise on-board clock circuitry works well enough for designs that do not need a highly accurate clock, such as the Calc design.

Figure 9.27 CLOCKGEN Schematic

The CLOCKGEN schematic contains an XC4000E library part, OSC4. This symbol represents the on-chip oscillator that generates nominal clock frequencies of 8 MHz, 500 KHz, 16 KHz, 490 Hz, and 15 Hz. The Calc design uses the 15-Hz output from this component when targeted for XC4000E family designs. The clock output from OSC4 buffers through a BUFG global clock buffer to minimize clock skew.

XC4000E family devices have eight on-chip clock buffers, one BUFGP (primary global buffer) and one BUFGS (secondary global buffer) in each corner of the device. Although you can use them for other purposes, you generally use BUFGPs to route externally-generated clock signals. BUFGSs have more flexibility, and can route any large fan-out net, even internally sourced fan-out nets. A BUFG symbol can represent either type of buffer, and allows the implementation software to choose the best type of global buffer for each situation. BUFG also facilitates design retargeting to other Xilinx device families because it can represent any type of global buffer in any family. The BUFG in the Calc design substitutes for a BUFGS during design implementation because the clock generates internally by the on-chip oscillator. See the Xilinx Libraries Guide and the Programmable Logic Data Book for more information on global clock buffers for Xilinx devices.

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