Step 4: Mapping the Design

The Design Manager manages the files created during the implementation process while the Flow Engine controls the implementation process itself. All the programs that run on a design are actually run by the Flow Engine based on the settings you supply in the various dialog boxes and templates.

1. Click the Flow Engine icon in the toolbox on the right side of the Design Manager.
   
   The Flow Engine is invoked using the flow settings specified earlier. The first stage of translating the input netlist and merging it into a single design file is complete. The design is now ready to be mapped into CLBs and IOBs. After mapping, the design is placed and routed. Finally, the configure stage creates a configuration bitstream that can be downloaded to the target system or formatted into a PROM programming file.
   
   The Flow Engine gives you complete control over how a design is processed. Typically you set all desired implementation options and run through the entire flow. However, to demonstrate the flexibility of the Flow Engine, and provide you with a working knowledge of the tool, this tutorial proceeds through each stage of the flow. For the Xilinx design flow, refer to the “Xilinx Design Flow” figure of the “Using the Software” chapter.
   
   

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   NOTE

   There are several ways to begin the implementation process. You can use the Flow Run and Flow Step commands, or you can use the equivalent control buttons, as shown in the following figure.

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   Figure 3.6 Control Panel

2. Click the Step control button to start the Map process.
   
   Even though a break point is not specified, the Flow Engine stops after the Map stage because only a single step is being run.
   
   Map performs the following functions.
   
   
   • Allocates CLB and IOB resources for all the basic logic elements in the design
     
     
   • Processes all location and timing constraints, performs target device optimizations, and runs a design rule check on the resulting mapped netlist
     
     

     Figure 3.7 Mapping Design

3. While Map is running, you can review the currently available reports using the Report Browser by selecting the following.
   
   Utilities Report Browser
   
   The Report Browser is displayed with the Translation report. The Map and Logic Level Timing Report files are created after Map is finished. New reports are denoted with a gold star in the upper left corner of the file icon.
   
   

   Figure 3.8 Report Browser after Running Map

4. Double-click on a report to review its output.
   
   
   • Translation Report - contains warning and error messages from the translation process. The translation process converts the input design netlist to the Xilinx NGD netlist as well as performs timing specification and logical design rule checks.
     
     
   • Map Report - contains information on how the target device resources are allocated, references to trimmed logic, and device utilization. For detailed information on the Map report, refer to the Development System Reference Guide.
     
     
   • Logic Level Timing Report - provides a summary analysis of your timing constraints based on block delays and estimates of route delays. This report is produced after map and prior to place and route.
     
     At this point in the Design Manger, the current version revision should have the status (Mapped, OK). The design has been mapped to the target architecture. The next step is evaluating paths in the design to ensure that they do not contain excessive block delays.