After the design is mapped, you can use the Logic Level Timing Report to evaluate the logical paths in the design. Because the design is not placed and routed yet, actual routing delay information is not available. The timing report describes the logical block delays and routing delays. The net delays that are provided are based on an optimal distance between blocks (also referred to as unplaced floors).
You can get a preliminary idea of how realistic your timing goals are by evaluating a design after the map stage. A rough guideline (known as the 50/50 rule) specifies that the block delays in any particular path will make up about 50% of the total path delay once the design is routed. This means that a path containing 10ns of block delay should meet a 20ns timing constraint after it has been placed and routed. If you have a high density design or use an architecture with fewer routing resources, your net delays may take more than 50% of the total path delay.
The following section from the Logic Level Timing Report represents a single path delay covered by the timing constraint specified in the user constraints file. This excerpt contains the following worst case path.
=========================================================================
Timing constraint: TS_CLOCK = PERIOD TIMEGRP “CLOCK” 20 nS HIGH 50.000% ;
44 items analyzed, 0 timing errors detected.
Minimum period is 6.352ns.
-------------------------------------------------------------------------
Slack: 13.648ns path N91 to N86 relative to
20.000ns delay constraint
Path N91 to N86 contains 5 levels of logic:
Path starting from Comp: CLB.K (from CLOCK_BUFGed)
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
CLB.YQ Tcko 1.470R N91
QOUT_reg<0>
CLB.G4 net (fanout=2) e 0.342R N91
CLB.COUT Topcy 1.600R N91
C17_C0_C1
CLB.CIN net (fanout=1) e 0.230R C17_N2
CLB.COUT Tbyp 0.140R N90
C17_C1_C2
CLB.CIN net (fanout=1) e 0.230R C17_N7
CLB.COUT Tbyp 0.140R N88
C17_C2_C2
CLB.CIN net (fanout=1) e 0.230R C17_N12
CLB.K Tsumc+Tick 1.970R N86
C17_C3_C2
c17_c3_c1_c0
QOUT_reg<6>
-------------------------------------------------------------------------
Total (5.320ns logic, 1.032ns route) 6.352ns (to CLOCK_BUFGed)
(83.8% logic, 16.2%% route)
-------------------------------------------------------------------------Once a design is mapped, you can roughly determine design performance by applying the 50/50 rule. For example, for the previous report excerpt, if you apply the 50% block (logic delay), 50% routing delay rule, the worst case path should be about 10ns after routing the design, given that the block levels currently contribute about 5ns (5.320ns). The timing constraint for this portion of the design is 20ns, leaving a slack time of 13.648ns. Therefore, this portion of the design is well within the timing specification.
The unplaced floors listed are actually estimates (indicated by the letter “e” next to the net delay) based on optimal placement of blocks. The total unplaced floors estimate for the design equals 1.032ns (3 x .23 + .342).
To obtain an even more accurate assessment of timing requirements, you can place a design without routing it. The resulting placed floors, which are based on optimistic routing estimates, provide an even more realistic account of net delays than the unplaced floors estimates from the mapped design. The placed estimates calculate an absolute minimum routing for each placement. For detailed information on how to do this, refer to the Development System Reference Guide.
If you do not generate a Logical Level Timing Report, PAR (place and route program) still processes a design based on the relationship between the block delays, floors, and timing specifications for the design. For example, if a PERIOD constraint of 8 ns is specified for a path, and there are block delays totaling 7 ns and unplaced floor net delays totalling 3 ns, PAR stops and generates an error message. In this case, PAR determines that the total delay (10 ns) is greater than the constraint placed on the design (8 ns), and appropriately fails. The Logic Level Timing Report provides an opportunity to determine any timing violation that may occur prior to running PAR.
