Creating Simulation Files

Once the design is implemented, a timing simulation can be performed to test the timing requirements and functionality of your design. Timing simulation can save considerable time by reducing time spent debugging test boards in the lab. Functional simulation can help you to further save time by uncovering design bugs before running Place and Route.

The Xilinx tools allow you to create simulation data after each major processing step. This means that you can create functional simulation netlists after the design has been merged together by NGDBuild in the Translate process, and timing simulation netlists after the design has been placed and routed by PAR. Additionally, you can create simulation data after the design has been mapped, or after the design has been placed but not routed.

Simulation data created after the design has only been mapped contains timing data based on the CLB and IOB block delays, and most net delays are zero.

Post-MAP simulation allows you to ensure that the design's current implementation will give the place and route software sufficient margin to route the design within your timing requirements.

Simulation data created after the design has been placed but not routed, contains accurate block delays and estimates for the net delays. Post-place simulation can be used as an incremental simulation step between post-MAP simulation and a complete post-route timing simulation.

Creating Timing Simulation Data

Follow these steps to create timing simulation data.

1. Select Design Implement from the Design Manager menu or click the Implement toolbar button. The Implement dialog box appears.
   
   
2. Select the Options button in the Implement dialog box. The Options dialog box appears.
   
   
3. Select the Produce Timing Simulation Data option.
   
   
4. In the same dialog box, click on the Edit Template button for simulation. Select the interface tab in the Simulation Template dialog box.
   
   
5. On the General tab, select one of the simulation netlist formats (EDIF, VHDL, or Verilog^®). If you selected EDIF, go to the EDIF tab, and select a CAE Vendor (Generic, ViewLogic, Mentor, or Foundation). If you select VHDL or Verilog, go to the VHDL/Verilog tab and select the options you want to use for simulation.
   
   
6. On the General tab, select the Correlate Simulation Data to Input Design option if you are using a simulation stimulus file or test fixture that was used for functional simulation, and contains signal names that were optimized out of your design during implementation.
   
   

With these options selected, the Flow Engine automatically creates a post-route simulation netlist in the selected format during the timing stage. To access the simulation netlist in the Design Manager, perform the following steps.

1. Select the revision.
   
   
2. Select Design Export. In the Export dialog box, select Timing Simulation Data and enter the export directory for the file.
   
   
3. Select OK. The listed netlist is copied to the selected directory. Use the netlist as input to your simulator to perform a timing simulation.
   
   

NOTE

For more information, see the Development System Reference Guide.

Creating Functional Simulation Data

Functional simulation netlists should be created using tools from the simulation vendor (Synopsys, Viewlogic, Mentor Graphics, and Cadence) and the Xilinx interface software. The implementation processes do not need to be invoked to create functional simulation netlists. However, if your design contains modules with varying netlist formats that the Xilinx interface software is unable to process, you can run NGDBuild on the design to create a single design_name.ngd and then create a simulation netlist using a translation tool: NGD2VHDL, NGD2VER, or NGD2EDIF. The following commands create a functional simulation netlist.

ngdbuild design_name

ngd2edif design_name