Downloading a Design

An implemented design can be downloaded directly from your PC or workstation, using the Hardware Debugger program and the XChecker cable.

The Hardware Debugger can download a bit file or a PROM file: MCS, EXO, or TEK.

For more information on downloading the Hardware Debugger or the XChecker cable, see the Hardware Debugger Reference/User Guide.

Creating a PROM

An FPGA or daisy chain of FPGAs can be configured from serial or parallel PROMs. The PROM File Formatter can create MCS, EXO, or TEK style files. The files are read by a PROM programmer that turns the image into a PROM.

A HEX file can also be used to configure an FPGA or a daisy chain of FPGAs through a microprocessor. The file is stored as a data structure in the microprocessor boot-up code.

In-Circuit Debugging

Once a design has been downloaded to an FPGA, snapshots of internal signal states can be captured and read using the Hardware Debugger program and the XChecker cable. You can display the signal states as waveforms in the Hardware Debugger. This capability allows you to test and debug your design in a real-time environment as it interfaces with components on your board. You can also control the states of your state machines, by controlling when clock edges are sent to your system clock input.

For more information on in-circuit debugging, the Hardware Debugger, or the XChecker cable, see the Hardware Debugger Reference/User Guide.

Advanced Implementation Flows

The place and route software, PAR, has features that allow it to process complex designs that have tight timing requirements and/or are difficult to route. PAR options can be varied in many different ways - this section shows the most common strategies.

Re-Entrant Route

PAR can take an implemented design as an input, and use it as the starting point for routing. If your design is placed but not routed, PAR will use the placement and just spend time routing the design. If your design is partially routed, PAR will use the existing placement and routing and only spend time routing the unrouted signals. If your design is completely placed and routed but not meeting timing specifications, PAR can start from where it left off and continue re-routing the design to come up with an implementation that meets your timing specifications.

As PAR is running, it continually updates the NCD file with its current placement and routing information. PAR can use a placed NCD file for re-entrant routing. To perform re-entrant routing, follow these steps.

1. In the Design Manager, select the implemented revision, and select the Flow Engine button in the toolbox.
   
   
2. In the Flow Engine, select the following.
   
   Setup FPGA Re-entrant
   
   
3. In the Setup Re-entrant Route dialog box, select the Allow Re-Entrant Routing button, which enables the re-entrant route options.
   
   
4. If meeting timing specifications is a critical goal for the route, select the Use the Timespecs button during re-entrant route. If meeting timing specifications is not critical, deselect the button because timing driven route takes longer than non-timing driven route.
   
   
5. Select the number of re-entrant routing passes. If Auto is selected, PAR performs routing iterations until it stops making significant progress or until your design constraints have been fully met.
   
   
6. Select the number and type of cleanup passes. Cleanup passes are run after the initial routing passes are complete. The effectiveness of the type of cleanup passes depends on the design, device, and constraints of the implementation. The best methodology is to select no more than three passes for each (in most cases, a single pass for each is sufficient), and use the PAR report to determine which is most effective. Then try using more cleanup passes of that style.
   
   
7. After you have selected your options, click OK. The Place and Route icon in the Flow Engine displays a loop back arrow and the Re-Entrant route label.
   
   

If you are specifying timing or location constraints, you may want to relax them to give PAR more flexibility. If you modify the UCF file, you must step the Flow Engine back and run Translation in order to incorporate the changes. Since your design is already implemented, step back to the beginning of Place & Route using the Step Backward button at the bottom of the Flow Engine, and then click the button to start again.