Appendix C

Processing Designs with LogiBLOX Components

The LogiBLOX utility gives designers access to a library of automatically generated, high-level functional modules to use in schematic-based or HDL designs. For Cadence designs, LogiBLOX generates both a functional simulation model for the block, as well as an NGO module ready for implementation as part of the overall design. Possible modules include adders, counters, accumulators, and memories. Currently LogiBLOX supports only the Spartan/XL, XC3000A/L, XC3100A/L, XC4000/E/EX/L/XL/XV and XC5200 architectures.

You must run LogiBLOX in standalone mode because it is not integrated into the Concept schematic editor. After generating the LogiBLOX module, you must create a symbol/body for the LogiBLOX module to integrate it into a schematic. For Verilog designs, direct LogiBLOX to generate a Verilog template that you can follow to instantiate the LogiBLOX into your Verilog design.

This appendix contains the following sections.

Generating the LogiBLOX module

For schematic based designs that also contain LogiBLOX components, you currently must run LogiBLOX in standalone mode to generate the required MOD and V (structural Verilog) files. You can then use the Concept genview command to generate a symbol body for the LogiBLOX module, and add the module to your schematic.

Use the following steps to generate the LogiBLOX module.

Start up LogiBLOX in standalone mode.

lbgui

A Setup popup appears if running LogiBLOX for the first time.

Figure C.1 LogiBLOX Setup Dialog Box
Specify the parameters for the LogiBLOX module.
1. Select “cadence” as the vendor and B<1> as the bus notation format.
2. Select your Project Directory (usually your working design directory) by clicking on the Project Directory tab on the Setup popup and either typing in the location of your project or using the Browse button to navigate to the desired directory
3. Select the Device Family (for example, XC4000EX) by clicking on the Device Family tab. Then click on the arrow button to select the desired device family from the list of supported device families.
4. Click on Options and select the desired simulation model (usually Structural Verilog). The Verilog netlist generates to support functional simulation, and later to generate the symbol body for the LogiBLOX module. Ensure the selection of the NGO file as the Implementation Netlist. Do not use the Component Declaration option on a top-level schematic.
  
  Figure C.2 Setup Dialog Box with Simulation Model Set
5. Click on OK to accept these settings. The LogiBLOX Module Selector appears.
  
  Figure C.3 LogiBLOX Module Selector
Enter a name for your module in the Module Name field. Select the Module Type by clicking on the down arrow button next to the Module Type field and selecting a module type from the list.
Specify a bus width by clicking on the down arrow button next to the Bus Width field or type a value in the Bus Width field.
Set the other parameters as desired, then click OK to generate the block and associated files. The LogiBLOX GUI Messages window appears.

Figure C.4 LogiBLOX GUI Messages Window
Click on Cancel when LogiBLOX has completed its run.

Creating a Symbol for the LogiBLOX module

If working on a schematic-based design, you must generate a symbol for your LogiBLOX module. You must create the symbol manually from within Concept using the genview command.

Make sure the Verilog file for your LogiBLOX module resides in your current directory. Start Concept, then enter the following command in the Concept command window to generate the body.

genview -i logiblox_module_name.v -v logic body \ verilog

Concept generates a body view for a module named logiblox_module_name from the Verilog netlist, puts it in the logical view for this module.
After generating the module, you must edit the resulting verilog.v file in the logic subdirectory of the new module directory. Add the following directive after the module declaration.

parameter cds_action = “ignore”;

For example, with a LogiBLOX module named “mycount,” genview does the following.
1. Creates an entry in your.wrk file for the module.
2. Creates a directory called “mycount” in your project directory.
3. Creates a subdirectory called “logic” under mycount and copies the LogiBLOX-generated mycount.v to mycount/logic/verilog.v.
4. Creates a symbol for the LogiBLOX module, mycount/body.1.1, instantiates and connects the new symbol in your design, and saves your design.
```
module mycount (load, up_dn, clk_en, clock, async_ctrl, term_cnt, d_in, q_out);
```
```
parameter cds_action=”ignore”; // <---- Add this line
```
```
       input load;
```
```
       input up_dn;
```
```
       input clk_en;
```
```
       input clock;
```
```
       input async_ctrl;
```
```
       output term_cnt;
```
```
       input [3:0] d_in;
```
```
       output [3:0] q_out;
```
```
....
```
Copy the NGO file for the Logiblox module to your design implementation directory (usually xilinx.run).

Netlisting the Design for the Functional Simulation

To generate a netlist for functional simulation, type the following command line.

concept2xil -family family_name -sim_only design_name

Family_name is the architecture.

Functional Simulation

To conduct HDL Direct Verilog Unified Library simulation manually, create a testbench file as described in the “Functional Simulation” chapter with the desired test vectors. Then invoke the simulation.

verilog +delay_mode_unit calcf.stim \ calc.v -f calcf.vf

The testbench file

After Verilog-XL finishes compiling your simulation commands, you can view the waveforms for the signals in your design. A waveform display application separate from Verilog-XL displays your simulation waveforms. Given the appropriate directives, Verilog-XL writes the waveform data to a simulation history directory (design.shm). The waveform viewer application (usually Simwave) reads this data from the simulation history database and displays the waveforms.

If you wish to view your simulation waveforms graphically while performing your functional simulation, you must add an “initial” block to the testbench file containing directives to create a simulation history database for the waveform viewer.

NOTE

NGD2VER adds the “initial” block to a stimulus template file (design.tv) by default. For pre-NGDBuild functional simulation flows, you must manually add this block to your testbench.

The following sample “initial” block adds Simulation History Manager support.

   initial
   begin
         $shm_open(“/home/user/cadence/calc/xilinx.run/ \
         calc.shm”);
         $shm_probe(“AS”);
   end

The $shm_open command creates the database directory, “calc.shm.” $shm_probe(“AS”) directs the simulation history manager to probe all signals, thus making them available for viewing in the waveform viewer.

Global Reset

Always toggle global reset at the beginning of a simulation to ensure that all flip-flops and latches initialize to a known state. See the “Setting Global Set/Reset and Tri-state Signals (FPGAs)” section of the “Design and Simulation Techniques” chapter for information about toggling global reset for XC3000A/L, XC3100A/L, XC4000/E/EX/L/XL/XV, XC5200, and XC9500 devices.

Appendix C

Processing Designs with LogiBLOX Components

Generating the LogiBLOX module

Figure C.1 LogiBLOX Setup Dialog Box

Figure C.2 Setup Dialog Box with Simulation Model Set