The xilinx.pff property filter file, located in $XILINX/cadence/data, specifies what properties SIR2EDF (called by CONCEPT2XIL) writes out to the EDIF netlist from your Concept schematic. The xilinx.pff file also specifies the format of these properties should when they write out to the EDIF netlist.
The xilinx.pff file has sections for symbol, pin, and net properties. Each section begins with a property section header record of the form, $xxx_PROP.
For symbol properties this header record is $SYM_PROP.
A list of properties that you can legally place on symbols in Concept follows the header.
Similarly, for pin properties, the header record for the pin property section is $PIN_PROP, and the header for net properties is $NET_PROP.
Each section also ends with a property section END record, $END.
Curly braces specify comments, as illustrated in the following example.
{ This is a comment in the property format file. }
You must provide a property specification record for every property that you want SIR2EDF to recognize and write out to the output EDIF file. The syntax of the property specification record follows.
property_name: "property_format" property_cast property_type;
The following example shows the syntax using string.
loc: LOC String NORMAL;
In the example, the loc property (found in the $SYM_PROP symbol properties section) has a property_name of loc. This property writes out to the EDIF file as LOC=value, where LOC is in upper case, and value is some alphanumeric string.
As with all Xilinx properties, the SIR2EDF type is NORMAL.
The following example shows the syntax using Boolean.
keep: KEEP Boolean NORMAL;
In this example, the Boolean property keep, from the $NET_PROPS section, attaches to a net. Specify its value as either TRUE or FALSE in the input design. When written out to the EDIF file, it appears as KEEP=TRUE.
The standard xilinx.pff property filter file shipped with the M1 Cadence Concept interface resides in $XILINX/cadence/data and is listed below.
The properties commented with the notation, {For lblox_syn} only support netlisting of Cadence Synergy Verilog designs which target LogiBLOX library components. Properties labelled as {Not entered by user} generate internally by Xilinx tools only.
XILINX.PFF File:
{Concept2xil property formatfile-4/19,1996,}
{Referenced rev1.2 of UVC and Attribute Description}
$SYM_PROP
ASYNC_VAL: ASYNC_VAL String NORMAL; {For lblox_syn}
ASYNC_COUNT: ASYNC_COUNT String NORMAL; {For lblox_syn}
SYNC_COUNT: SYNC_COUNT String NORMAL; {For lblox_syn}
BUS_WIDTH: BUS_WIDTH String NORMAL; {For lblox_syn}
COUNT_TO: COUNT_TO String NORMAL; {For lblox_syn}
C_VALUE: C_VALUE String NORMAL; {For lblox_syn}
DECODEMASK: DECODEMASK String NORMAL; {For lblox_syn}
DEF: DEF String NORMAL; {For lblox_syn}
DELAY: DELAY String NORMAL; {For lblox_syn}
DEPTH: DEPTH String NORMAL; {For lblox_syn}
DIVIDE_BY: DIVIDE_BY String NORMAL; {For lblox_syn}
DUTY_CYCLE: DUTY_CYCLE String NORMAL; {For lblox_syn}
ENCODING: ENCODING String NORMAL; {For lblox_syn}
FLOAT_VAL: FLOAT_VAL String NORMAL; {For lblox_syn}
INPUT_BUSSES: INPUT_BUSSES String NORMAL; {For lblox_syn}
IN_TYPE: IN_TYPE String NORMAL; {For lblox_syn}
INVMASK: INVMASK String NORMAL; {For lblox_syn}
PAD_LOC: PAD_LOC String NORMAL; {For lblox_syn}
MEMFILE: MEMFILE String NORMAL; {For lblox_syn}
MODTYPE: MODTYPE String NORMAL; {For lblox_syn}
OPTYPE: OPTYPE String NORMAL; {For lblox_syn}
OUT_TYPE: OUT_TYPE String NORMAL; {For lblox_syn}
REGISTERED: REGISTERED String NORMAL; {For lblox_syn}
REG_OUT: REG_OUT String NORMAL; {For lblox_syn}
SHIFT_TYPE: SHIFT_TYPE String NORMAL; {For lblox_syn}
SLEWRATE: SLEWRATE String NORMAL; {For lblox_syn}
STYLE: STYLE String NORMAL; {For lblox_syn}
SYNC_VAL: SYNC_VAL String NORMAL; {For lblox_syn}
add: ADD String NORMAL; {Not entered by user.}
alu: ALU String NORMAL; {Not entered by user.}
base: BASE String NORMAL; {3k only}
blknm: BLKNM String NORMAL;
bufg: BUFG String NORMAL; {7k,9k}
clock_out: CLOCK_OUTPUT Boolean NORMAL; {4KXV only}
config: CONFIG String NORMAL;
cymode: CYMODE String NORMAL; {Not entered by user.}
decode: DECODE Boolean NORMAL;
d_invert: D_INVERT String NORMAL; {Not entered by user.}
divide1_by: DIVIDE1_BY Integer NORMAL;
divide2_by: DIVIDE2_BY Integer NORMAL;
double: DOUBLE Boolean NORMAL;
drive: DRIVE Integer NORMAL; {4KXV only}
eqn: EQN String NORMAL; {Not entered by user.}
equate_f: EQUATE_F String NORMAL;
equate_g: EQUATE_G String NORMAL;
fast: FAST Boolean NORMAL;
file: FILE String NORMAL;
grp01: GRP01 String NORMAL; {Timegroup}
grp02: GRP02 String NORMAL;
grp03: GRP03 String NORMAL;
grp04: GRP04 String NORMAL;
grp05: GRP05 String NORMAL;
grp06: GRP06 String NORMAL;
grp07: GRP07 String NORMAL;
grp08: GRP08 String NORMAL;
grp09: GRP09 String NORMAL;
grp010: GRP010 String NORMAL;
hblknm: HBLKNM String NORMAL;
hu_set: HU_SET String NORMAL;
init: INIT String NORMAL;
libver: LIBVER String NORMAL; {Not entered by user.}
io: IO Boolean NORMAL;
loc: LOC String NORMAL;
lowpwr: LOWPWR String NORMAL;
map: MAP String NORMAL;
meddelay: MEDDELAY Boolean NORMAL;
minim: MINIM String NORMAL;
nodelay: NODELAY Boolean NORMAL;
opt: OPT String NORMAL;
optimize: OPTIMIZE String NORMAL;
opt_effort: OPT_EFFORT String NORMAL;
osc: OSC String NORMAL; {5k only}
part: PART String NORMAL;
prohibit: PROHIBIT String NORMAL;
pwr_mode: PWR_MODE String NORMAL;
reg: REG String NORMAL; {Not entered by user.}
rloc: RLOC String NORMAL;
rloc_origin: RLOC_ORIGIN String NORMAL;
rloc_range: RLOC_RANGE String NORMAL;
slow: SLOW Boolean NORMAL;
tig: TIG String NORMAL;
tnm: TNM String NORMAL;
ts01: TS01 String NORMAL; {Timespec}
ts02: TS02 String NORMAL;
ts03: TS03 String NORMAL;
ts04: TS04 String NORMAL;
ts05: TS05 String NORMAL;
ts06: TS06 String NORMAL;
ts07: TS07 String NORMAL;
ts08: TS08 String NORMAL;
ts09: TS09 String NORMAL;
ts10: TS10 String NORMAL;
u_set: U_SET String NORMAL;
use_rloc: USE_RLOC Boolean NORMAL;
wireand: WIREAND Boolean NORMAL;
inreg: INREG String NORMAL; {5k ONLY}
outreg: OUTREG String NORMAL; {5k ONLY}
bsreadback: BSREADBACK String NORMAL; {For Config Symbol Only}
bsreconfig: BSRECONFIG String NORMAL; {For Config Symbol Only}
configrate: CONFIGRATE String NORMAL; {For Config Symbol Only}
crc: CRC String NORMAL; {For Config Symbol Only}
donepin: DONEPIN String NORMAL; {For Config Symbol Only}
doneactive: DONEACTIVE String NORMAL; {For Config Symbol Only}
gsrinactive: GSRINACTIVE String NORMAL; {For Config Symbol Only}
inputs: INPUTS String NORMAL; {For Config Symbol Only}
lengthcount: LENGTHCOUNT String NORMAL; {For Config Symbol Only}
m0pin: M0PIN String NORMAL; {For Config Symbol Only}
m1pin: M1PIN String NORMAL; {For Config Symbol Only}
m2pin: M2PIN String NORMAL; {For Config Symbol Only}
oscillator: OSCILLATOR String NORMAL; {For Config Symbol Only}
oscclk: OSCCLK String NORMAL; {For Config Symbol Only}
outputs: OUTPUTS String NORMAL; {For Config Symbol Only}
outputsactive: OUTPUTSACTIVE String NORMAL; {For Config Symbol Only}
progmode: PROGMODE String NORMAL; {For Config Symbol Only}
progpin: PROGPIN String NORMAL; {For Config Symbol Only}
readabort: READABORT String NORMAL; {For Config Symbol Only}
readback: READBACK String NORMAL; {For Config Symbol Only}
readcapture: READCAPTURE String NORMAL; {For Config Symbol Only}
readclk: READCLK String NORMAL; {For Config Symbol Only}
startupclk: STARTUPCLK String NORMAL; {For Config Symbol Only}
startupmode: STARTUPMODE String NORMAL; {For Config Symbol Only}
synctodone: SYNCTODONE String NORMAL; {For Config Symbol Only}
userstring: USERSTRING String NORMAL; {For Config Symbol Only}
$END.
$PIN_PROP
tig: TIG String NORMAL;
tnm: TNM String NORMAL;
tspec: TSPEC String NORMAL;
$END.
$NET_PROP
bufg: BUFG String NORMAL; {7k,9k}
collapse: COLLAPSE Boolean NORMAL;
cymode: CYMODE String NORMAL;
decode: DECODE Boolean NORMAL;
divide1_by: DIVIDE1_BY Integer NORMAL;
divide2_by: DIVIDE2_BY Integer NORMAL;
double: DOUBLE Boolean NORMAL;
fast: FAST Boolean NORMAL;
hblknm: HBLKNM String NORMAL;
hu_set: HU_SET String NORMAL;
init: INIT String NORMAL;
io: IO Boolean NORMAL;
keep: KEEP Boolean NORMAL;
loc: LOC String NORMAL;
maxdelay: MAXDELAY String NORMAL;
maxskew: MAXSKEW String NORMAL;
noreduce: NOREDUCE Boolean NORMAL;
offset: OFFSET String NORMAL;
opt: OPT String NORMAL;
period: PERIOD String NORMAL;
pwr_mode: PWR_MODE String NORMAL;
slow: SLOW Boolean NORMAL;
tig: TIG String NORMAL;
tpsync: TPSYNC String NORMAL;
tpthru: TPTHRU String NORMAL;
tspec: TSPEC String NORMAL;
tnm: TNM String NORMAL;
wireand: WIREAND Boolean NORMAL;
f: F Boolean NORMAL; {Net Flag Attributes}
s: S Boolean NORMAL; {Net Flag Attributes}
h: H Boolean NORMAL; {Net Flag Attributes}
p: P Boolean NORMAL; {Net Flag Attributes}
x: X Boolean NORMAL; {Net Flag Attributes}
$END.