This appendix contains an annotated test fixture template as well as three sample test fixtures illustrating how the following types of simulation specify and exercice the global GSR and GTS signals.
This manual uses the terms “testbench” and “test fixture” synonymously.
This Appendix contains the following sections.
// NGD2VER VERILOG Test Fixture Template
// Design file: calc.ngd
// Date:Sat May 17 00:07:34 1997 // ATTENTION: This file was created by NGD2VER and may therefore be
// overwritten by subsequent runs of NGD2VER. Xilinx recommends that you
// copy this file to a new name, or 'paste' this text into another file,
// to avoid accidental loss of data. // The timescale directive specifies the default time unit used for the
// simulation. In this case, it is 1ns, with a precision of 1 ps (.001ns) `timescale 1 ns/1 ps // The module, "test", is the testbench module. Within it, we first see
// a listing of all the OUTPUTs of the design, which are declared as
// "wires" (ofl, a, b, c, d, e, f, g, gauge[3:0], stackled[3:0], and
// switch[7:0]. These are followed by the inputs, which are declared with
// data type, "reg", for "register". In this case, the only input is an // 8-bit bus named "switch[7:0]". // An instance of the design, "calc", is also instantiated within the
// "test" module, with an instance name of "uut". module test;
wire ofl;
reg notgblreset;
wire g;
wire f;
wire e;
wire d;
wire c;
wire b;
wire a;
wire [3:0] gauge;
wire [3:0] stackled;
reg [7:0] switch;
// To properly simulate your design containing a Startup component,
// be sure to do the following at the beginning of your simulation:
//
// 1. Toggle your GSR port to initialize all registers.
//
// 2. Deactivate your global tri-state (GTS) control signal.
//
calc uut ( .ofl (ofl) , .notgblreset (notgblreset) , .g (g) , .f (f)
, .e (e) , .d (d) , .c (c) , .b (b) , .a (a) , .gauge (gauge)
, .stackled (stackled) , .switch (switch) ); // The "timeformat" system task specifies how time information for the
// $display and $monitor commands is to be formatted when displayed by
// Verilog-XL. The first number represents the "unit" value, the second,
// the precision number, followed by the suffix string to be displayed (in
// this case, "ns"),and lastly, the minimum width of the field for the
// string (12 characters, in this example).Reference: Verilog-XL
// Reference Manual. initial begin
$timeformat(-9,3,"ns",12); // Support for the Cadence waveform viewer is added here by calling the
// $shm_open task, which directs Verilog-XL to create a Simulation History
// Manager (SHM) database called "routed.shm". The waveform viewer
// (SIMWAVES) displays the waveform information that has been
// written to .shm database. // The $shm_probe ("AS") system task tells the Verilog-XL simulator
// which signal changes are to be recorded in the Simulation History
// Manager database. In this case, "AS" specifies that ALL signal changes
// are to be recorded. $shm_open("/export/vol1/m1.0/testing/m1tutorial/newsch/xilinx.run/calcf.shm");
$shm_probe("AS");
end // The "initial" block here displays the transitions of all the external
// signals of the design in vertical columnar format. initial begin
$display(" T ongfedcbaggggssssssssssss");
$display(" i fo aaaattttwwwwwwww");
$display(" m lt uuuuaaaaiiiiiiii");
$display(" e g ggggcccctttttttt");
$display(" b eeeekkkkcccccccc");
$display(" l [[[[llllhhhhhhhh");
$display(" r 3210eeee[[[[[[[[");
$display(" e ]]]]dddd76543210");
$display(" s [[[[]]]]]]]]");
$display(" e 3210 ");
$display(“ t ]]]] “); // The $monitor system task specifies the format by which all signal
// changes will appear when displayed in text format. In this example,
// "gauge", "stackled", and "switch" are displayed in bus format. $monitor("%t",$realtime,, ofl, notgblresetg, f, e, d, c, b, a, "%b", gauge, "%b", stackled, "%b", switch ); end initial begin
#100
notgblreset = 0 ;
switch = 0 ; // ########## USER-SPECIFIED test vectors can be added here #############
// ########## USER-SPECIFIED test vectors can be added here #############
// ########## USER-SPECIFIED test vectors can be added here #############
// ######### USER-SPECIFIED test vectors can be added here ############# #1000 $stop; #1000 finish;
end endmoduleThis text fixture, for a design called count_invstartup, contains a STARTUP block with only the GSR pin connected to a pad via a signal called “mygsr.” The net connected to the GSR pin is “gsrin.”
// NGD2VER VERILOG TestFixture Template
// Design file: count_startup.ngd
// Date:Thu May 15 21:15:11 1997 // ATTENTION: This file was created by NGD2VER and may therefore be
// overwritten by subsequent runs of NGD2VER. Xilinx recommends that you
// copy this file to a new name, or 'paste' this text into another file,
// to avoid accidental loss of data. `timescale 1 ns/1 ps module test; reg mygsr;
reg clock;
wire [15:0] q;
wire [7:0] qpp; // To properly simulate your design containing a Startup component,
// be sure to do the following at the beginning of your simulation: // 1. Toggle your GSR port to initialize all registers.
// 2. Deactivate your global tri-state (GTS) control signal. `define GSR_SIGNAL test.uut.gsrin // For HDL Direct / Unified Library simulation, you may optionally create
// a GTS control signal and connect it to the GTS_SIGNAL declared
// in the Unified Library simulation models. wire GTS;
`define GTS_SIGNAL test.GTS count_invstartup uut ( .mygsr (mygsr) , .clock (clock) , .q (q) , .qpp (qpp) ); initial begin $timeformat(-9,3,"ns",12);
$shm_open("count_star.shm");
$shm_probe("AS"); end initial begin $display(" T mGGcqqqqqqqqqqqqqqqqqqqqqqqq"); $display(" i ySTl[[[[[[[[[[[[[[[[pppppppp"); $display(" m gRSo1111119876543210pppppppp"); $display(" e s c543210]]]]]]]]]][[[[[[[["); $display(" r k]]]]]] 76543210"); $display(" ]]]]]]]]"); $monitor("%t",$realtime,, mygsr, `GSR_SIGNAL, `GSR_SIGNAL, clock, "%b", q, "%b", qpp ); // $monitor("%t",$realtime,, mygsr, `GSR_SIGNAL, `GTS_SIGNAL, clock, "%b", q, "%b", qpp ); end always #20 clock = ~clock; initial begin mygsr = 0 ;
clock = 1 ;
force `GTS_SIGNAL = 0; #100 mygsr = 1 ; #3000 $stop; // #1000 $finish; end endmoduleThis text fixture, for the design, count_invstartup, contains a STARTUP block with only the GSR pin connected to a pad via a signal called “mygsr.” The net connected to the GSR pin is “gsrin.”
In this example, the GTS pin on the STARTUP block is not connected.
Use this sample test fixture for the following types of simulations.
// NGD2VER VERILOG TestFixture Template
// Design file: count_invstartup.ngd
// Date:Thu May 15 21:15:11 1997 // ATTENTION: This file was created by NGD2VER and may therefore be
// overwritten by subsequent runs of NGD2VER. Xilinx recommends that you
// copy this file to a new name, or 'paste' this text into another file,
// to avoid accidental loss of data. `timescale 1 ns/1 ps module test; reg mygsr; reg clock; wire [15:0] q; wire [7:0] qpp; // To properly simulate your design containing a Startup component,
// be sure to do the following at the beginning of your simulation: // 1. Toggle your GSR port to initialize all registers. // // 2. Deactivate your global tri-state (GTS) control signal. // //`define GSR_SIGNAL test.uut.gsrin
// Comment out this definition // wire GTS;
// `define GTS_SIGNAL test.GTS `define GTS_SIGNAL test.uut.GTS count_invstartup uut ( .mygsr (mygsr) , .clock (clock) , .q (q) , .qpp (qpp) ); initial begin $timeformat(-9,3,"ns",12); $shm_open("count_star.shm"); $shm_probe("AS"); end initial begin $display(" T mGGcqqqqqqqqqqqqqqqqqqqqqqqq"); $display(" i ySTl[[[[[[[[[[[[[[[[pppppppp"); $display(" m gRSo1111119876543210pppppppp"); $display(" e s c543210]]]]]]]]]][[[[[[[["); $display(" r k]]]]]] 76543210"); $display(" ]]]]]]]]"); $monitor("%t",$realtime,, mygsr, test.uut.GSR, `GTS_SIGNAL, clock, "%b", q, "%b", qpp ); end always #20 clock = ~clock; initial begin mygsr = 0 ; clock = 1 ; force `GTS_SIGNAL = 0; #100 mygsr = 1 ; #3000 $stop; // #1000 $finish; end endmoduleWhen a design does not contain a STARTUP block, you can often use the same test fixture for Unified Library functional simulation, post-NGDBuild functional simulation, as well as timing simulation.
// NGD2VER VERILOG TestFixture Template
// Design file: count_top.ngd
// Date:Fri May 16 18:59:39 1997 // ATTENTION: This file was created by NGD2VER and may therefore be
// overwritten by subsequent runs of NGD2VER. Xilinx recommends that you
// copy this file to a new name, or 'paste' this text into another file,
// to avoid accidental loss of data. `timescale 1 ns/1 ps module test; reg clock; wire [15:0] q; wire [7:0] qpp; reg GSR; `define GSR_SIGNAL test.GSR reg GTS; `define GTS_SIGNAL test.GTS count_top uut ( .clock (clock) , .q (q) , .qpp (qpp) ); initial begin $timeformat(-9,3,"ns",12); $shm_open("count_topf.shm"); $shm_probe("AS"); end initial begin $display(" T GGcqqqqqqqqqqqqqqqqqqqqqqqq"); $display(" i STl[[[[[[[[[[[[[[[[pppppppp"); $display(" m RSo1111119876543210pppppppp"); $display(" e c543210]]]]]]]]]][[[[[[[["); $display(" k]]]]]] 76543210"); $display(" ]]]]]]]]"); $monitor("%t",$realtime,, `GSR_SIGNAL, `GTS_SIGNAL, clock, "%b", q, "%b", qpp ); end always #20 clock = ~clock; initial begin clock = 0 ; `GSR_SIGNAL = 1; `GTS_SIGNAL = 0; #100 `GSR_SIGNAL = 0; #3000 $stop; // #1000 $finish; end endmodule