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Demonstration Board Operation

This section describes how to use the XChecker download cable with the FPGA Demonstration Board and Hardware Debugger software for device configuration. Explicit cable connection information is included in the “Cable Hardware” chapter.

The information in this section applies to both the XC3020A and the XC4003E devices. However, for clarity references are only made to the XC4003E FPGA.

NOTE

The Parallel Cable III can also be used for FPGA configuration. For Parallel Cable III connection information, refer to the “Parallel Cable III” section of the “Cable Hardware” chapter.

Demonstration Designs

Demonstration designs are supplied with Xilinx Foundation™ and Alliance Series™ software. You can view or edit the demonstration designs. Before editing, you must compile the input files with your design implementation software.

These example designs incorporate the ability of the XC4003E to build ROM out of function generators. The ROM macros store a sequence of patterns that are displayed on the 7-segment displays and the LED bar graphs of the FPGA Demonstration board.

Please read the text files that accompany these designs. Design schematics are available by calling the Xilinx Technical Support Hotline. You can also access schematics through the Xilinx web site, located at (http://www.xilinx.com).

Design Downloading Checklist

You must follow the recommended design flow to assure proper operation. Make backups before making changes to any demonstration design files. The following checklist.

  1. Produce a routed design, design_name using a design entry tool and the appropriate place and route tool.

    If you want a global Reset signal in your XC4000 designs, you must include the Startup symbol in your design and select the location of the RESET pin. Attach pin 56 to an inverter and the GSR pin on the Startup symbol. GSR is active-High so you must include an inverter between the pad and the Startup symbol.

  2. Generate a bitstream for the design, design_name.bit with the appropriate configuration options using the BitGen program.

  3. Optionally, create a PROM File.

  4. Generate a PROM file (design_name.mcs, design_name.tek, or design_name.exo) using the PROMGen program. This step is optional since the XChecker and Hardware Debugger software can use the design.bit file as input.

  5. Connect the XChecker cable to your host system.

  6. Connect the XChecker cable to your target system.

    The XChecker cable draws its power from the target system through the VCC and GND wires. Therefore, power to the XChecker cable and the target FPGA must be stable. Do not connect the XChecker cable pins to any signals before connecting VCC and ground to the FPGA Demonstration Board.

    When you use the XChecker cable to download, only one of the two-keyed connectors are needed.

  7. Connect XChecker to J1 (for the XC3020A) and J2 (for the XC4003E) on the FPGA Demonstration Board.

  8. Set the mode switches.

    When you use the XChecker cable, the M0, M1, and M2 switches must be on. This setting causes the device to be in the serial slave mode. Refer to the “Configuring the XC3020A and XC4003E in a Daisy Chain from the XChecker/Parallel Cable III” table for the switch settings necessary to configure a daisy chain.

  9. Power up the target system.

  10. Start your software package.

For information on starting the Hardware Debugger software, see the “Starting Hardware Debugger” section.

Loading with a Configuration PROM

If you already have a design burned in a PROM, skip to step 5. You can also view or edit the demonstration designs supplied with the Xilinx software tools.

NOTE

Make backups before making changes to any demonstration design files.

  1. Place and route the design.

    Produce a routed design, design_name using a design entry tool and the appropriate place and route tool.

  2. Generate a configuration bitstream for the design, design_name.bit with the appropriate configuration options using the BitGen program.

  3. Create a PROM file.

    Generate a PROM file (design_name) using the PROMGen program. See the PROMGen documentation in the Development System Reference Guide to create a PROM file.

    NOTE

    The XC1700 series of configuration serial PROMs must be programmed with the reset polarity set for active-Low.

  4. Place the PROM on the FPGA Demonstration Board.

    After you have a PROM that has a configuration bitstream burned into it, place it into the FPGA Demonstration Board with power off. Use the appropriate demonstration board socket for your device.

  5. Set the mode switches.

    When you use the serial PROMs, the M0, M1, and M2 switches must be off. This setting causes the device to be in the active master serial mode. Set the MPE, SPE, and RST switches to the desired positions. Refer to the“Configuring the XC3020A and XC4003E in a Daisy Chain from the Serial PROM (Single Program)” table and the “Configuring the XC3020A and XC4003E in a Daisy Chain from the Serial PROM (Multiple Program)” table for switch settings required to configure a daisy chain.

  6. Load the FPGA.

  7. After you insert the PROM into the socket and set the configuration switches, apply power to the FPGA Demonstration Board.

    This step configures the FPGA; when the Done pin goes High, it indicates that the design logic is active.

  8. Start your configuration software.

For information on starting the Hardware Debugger software, see the following section.

Starting Hardware Debugger

The following section includes a checklist for opening the Hardware Debugger software. For further information, consult the Hardware Debugger Reference/User Guide.

  1. Open your Alliance or Foundation software.

  2. From within Xilinx Design Manager (version M1.0 or later), select Hardware Debugger from the tools menu. You can also start the Hardware Debugger from the operating system prompt by entering the following command.

    hwdebugr design_name

    When you start the Hardware Debugger, the port where the cable is plugged in is located, and the baud rate is set to the maximum allowed by the platform.

  3. A message window indicates that the FPGA design is loading. When loading is complete, the Hardware Debugger indicates that the Done pin went High. At this point, the loaded bit file functions as designed.

Tutorials

NOTE

Updated tutorials will be available after June 30, 1998 from the Xilinx Web site and on the AppLINX CD. The Web site location is (http://www.xilinx.com/support/techsup/tutorials). Please contact your local Sales Representative for a copy of the AppLINX CD.

Calculator tutorial designs for Mentor® and Cadence are available on the Xilinx CAE Interface CD-ROM at the following locations.

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