Creating Timing Specifications

The timing constraints issued to Synopsys to control the synthesis process pass through to the design implementation tools to control the place and route process. To get the best possible results, make these constraints realistic and achievable.

During the synthesis of your design, area and timing constraints can impact implementation almost as much as changes made to your HDL code. Carefully apply area and timing constraints. During the implementation of your design, timing constraints have a direct impact on run time and performance verification. For example, the run time required to find a place and route solution to support the 40 MHz operation of a design takes longer than that required to find a 4 MHz solution. Meaningful and detailed timing constraints also allow the design implementation tools to report the status of your design's timing in terms of your timing goals.

The DC2NCF program converts timing constraints applied to your design in the Synopsys environment to equivalent constraints that control the Xilinx place and route process. Automatic translation of these constraints offers an advantage because you do not need to apply the constraints twice (once for Synopsys and again for Xilinx). The constraints used by Xilinx are equivalent to those applied with Synopsys.

DC2NCF supports translation of the following Synopsys timing constraints.

create_clock
set_input_delay
set_output_delay
set_max_delay
set_false_path

If you have additional Synopsys timing constraint commands in your Synopsys script file, DC2NCF issues a warning and does not translate them.

DC2NCF translates a Synopsys DC file to a Xilinx Netlist Constraints File (NCF). The DC file is a Synopsys script file containing the constraints that have been applied to your design. EDIF2NGD or XNF2NGD reads the output NCF file. The constraints in the NCF file become part of the NGO file produced by EDIF2NGD or XNF2NGD. The following example shows how to translate a DC file to an NCF file.

dc2ncf dc_file[.dc] [-o ncf_file[.ncf]] [-w | -wildcard]

When you specify the -w option, DC2NCF creates an NCF file with wildcards. The -w option can significantly increase run time. An NCF backup file without wildcards saves as ncf_file.ncf_orig. To use the original file without wildcards, rename ncf_file.ncf_orig to ncf_file.ncf.

Following the DC2NCF Design Flow

Before running DC2NCF, apply your timing constraints to your design and then compile it. Also, when using FPGA Compiler for XC4000E/L/EX/XL/XLA/XV designs, run the Replace FPGA command, then create a netlist and a corresponding script file that contains the constraints.

DC2NCF can incorrectly translate the timing constraint commands in user-created script files. Always generate script files as described in the following sections using either DC Shell or Design Analyzer.

Creating the Netlist and Script File (Design Compiler)

You can use DC Shell or Design Analyzer to create your design's netlist and the Synopsys constraints script file.

From the DC Shell command line, perform the following steps.

Flatten your design's hierarchy by entering the following.

ungroup -all -flatten
Enter the following to create the netlist.

write -format edif -hierarchy -output \ design_name.sedif

The “\” indicates you issue this command in one line, not two as presented here.
To write your design's constraints as a Synopsys script file, enter the following.

write_script > design_name.dc

From Design Analyzer, perform the following steps.

Select File Save As

The Save File dialog box appears.
Select the EDIF option in the File Format field. Change the extension to .sedif in the File Name field.
Turn off the Save All Designs in Hierarchy option.
Select OK.
Select the following to get the command window.

Setup Command Window
At the command window prompt, enter the following.

ungroup -all -flatten
To write your design's constraints as a Synopsys script file, select the design setup function.

File Save Info Design Setup

The Save Design Setup dialog box appears.
Select OK.

Creating the Netlist and Script File (FPGA Compiler)

Before you create the netlist or the constraints file, you must flatten any hierarchy in your design. Flattening your design removes hierarchy information from the Synopsys internal database. However, the hierarchical net names and instance names assigned to objects during compilation are retained and written to the output netlist. The Xilinx software reconstructs most of your design's hierarchy from the information contained in the instance names and net names.

Use the DC Shell or Design Analyzer to flatten your design, create your design's netlist, and create the Synopsys constraints script file.

To flatten your design's hierarchy prior to writing a netlist and constraints file from the DC Shell command line, perform the following steps.

Enter the following to flatten the design.

ungroup -flatten -all
To create your design's netlist in XNF format, enter the following.

write -format xnf -output design_name.sxnf
To write your design's constraints as a Synopsys script file, enter the following.

write_script > design_name.dc

To flatten your design's hierarchy from Design Analyzer, perform the following steps.

Select Setup Command Window

The Command Window appears.
Enter the following at the command line.

ungroup -all -flatten
Select File Save As

The Save File dialog box appears.
Select the XNF option in the File Format field. Change the .xnf extension to .sxnf in the File Name field.
Turn off the Save All Designs in Hierarchy option.
Select OK.
To write your design's constraints as a Synopsys script file, select the design setup function.

File Save Info Design Setup

The Save Design Setup dialog box appears.
Select OK.

Understanding DC2NCF Translation Limitations

This section lists the Synopsys commands you can use to create timing specifications for your Xilinx designs and provides information about DC2NCF support for the Synopsys timing commands.

Limitations of Create Clock

The Create Clock command applies a constraint of period_value nanoseconds to all paths between the registers reached by tracing forward from the entries on the port_or_pin_list. A general description of the Create Clock command follows.

Syntax

create_clock [port_or_pin_list] [-name clock_name] \ [-period period_value] [-waveform edge_list]
Virtual clocks

DC2NCF does not support virtual clocks and therefore does not support Create Clock statements without a port_or_pin_list.
Complex clock waveforms

Since DC2NCF only supports single-cycle clock waveforms, the waveform edge_list variable can only contain two values.
Targets for Create Clock

DC2NCF translates the Create Clock command into the Xilinx PERIOD constraint, applied to chip-level input (or bidirectional) ports and to the outputs of primitive Xilinx cells. Therefore, the port_or_pin_list variable can only include references to these types of nodes.

Limitations of Set Input Delay and Set Output Delay

The Set Input Delay command specifies that data arriving at the inputs listed in the port_or_pin_list delays externally by the number of nanoseconds specified by delay_value.

The Set Output Delay command specifies that data arriving at the outputs listed in the port_or_pin_list drives into an external delay of delay_value nanoseconds.

Therefore, constrain internal paths starting (Set Input Delay) or ending (Set Output Delay) at any of the nodes listed in the port_or_pin_list more tightly to accommodate these external margins.

Syntax

set_input_delay delay_value\ [-clock clock_name [-clock_fall] \ [-level_sensitive]] \ [-rise | -fall] [-max] [-min] [-add_delay] \ port_or_pin_list

set_output_delay delay_value\ [-clock clock_name [-clock_fall] \ [-level_sensitive]] \ [-rise | -fall] [-max] [-min] \ [-add_delay] port_or_pin_list
Minimum delay constraints

Normally, the -min switch specifies the minimum value of an external delay. However, because Xilinx allows constraining only maximum delays within a device, DC2NCF does not support the -min switch. (This also makes the -max switch redundant.)
Rising and falling constraints

Because Xilinx does not categorize timing paths by their sensitivity to rising or falling edges at their inputs, DC2NCF does not support the Rise, Fall, and Clock_fall switches.
Latch versus register path sources

Because Xilinx does not compute path delays differently depending on the type of sequential cell that sources the path, DC2NCF does not support the Level Sensitive switch.
Targets for Set Input Delay and Set Output Delay

DC2NCF translates the Set Input Delay and Set Output Delay commands into the Xilinx OFFSET constraint, applied only to chip-level input or bidirectional ports (Set Input Delay) and output or bidirectional ports (Set Output Delay). Therefore, the port_or_pin_list variable can only include references to these types of objects. For example, external delays applied to the ports of hierarchical sub-modules do not translate.

Arrival times specified with the -clock clock_name switch must conform to the OFFSET command usage restrictions. Although the clock referred to by clock_name can contain chip-level I/O ports and cell pin-names, the translation of the Set Input Delay and Set Output Delay commands applies only to those clocks assigned to chip-level I/O ports. Therefore, specify arrival times only with respect to clocks applied externally (not internally).

Limitations of Set Max Delay and Set False Path

The Set Max Delay command specifies the upper delay limits for all paths that start at nodes listed in the from_list and end at nodes listed in the to_list.

The Set False Path command specifies that paths starting at nodes listed in the from_list and ending at nodes listed in the to_list are not significant for timing.

Syntax

set_max_delay delay_value [-rise | -fall] \ [-from from_list] [-to to_list] \ [-group_path group_name] [-reset_path]

set_false_path [-rise | -fall] \ [-setup | -hold] [-from from_list] [-to to_list] \ [-reset_path]
Rising and falling constraints

Because Xilinx does not categorize timing paths by their sensitivity to rising or falling edges at their inputs, DC2NCF does not support the Rise and Fall switches.
Path Grouping (Set Max Delay)

Synopsys uses a path grouping mechanism for directing the logic optimizer to certain areas of your design; this does not impact the resulting timing specification. Therefore, DC2NCF does not support the -group_path group_name switch.
Iterative path constraints

You can use the -reset_path switch prior to compilation to remove a constraint between the indicated path start and end points. Because DC2NCF reads script files generated after compilation, the -reset_path switch does not appear in the output script file. Therefore, DC2NCF does not support the -reset_path switch.
Targets for Set Max Delay and Set False Path

DC2NCF translates the Set Max Delay and Set False Path commands to several Xilinx timing constraint commands, adding elements in the from_list and the to_list to Xilinx timegroups using the TIMEGROUP command. Issue a constraint between the two timegroups using the FROM:<group>:TO:<group>:<delay>ns (Set Max Delay) and FROM:<group>:TO:<group>:TIG; (Set False Path) commands.

Xilinx allows only certain nodes for path start points and end points. These nodes include RAMs, latches, registers and I/O ports. Therefore, from_list and to_list can only include references to these types of objects.
The Replace FPGA Command removes Set Max Delay and Set False Path constraints (FPGA Compiler only)

The Replace FPGA command removes any Set Max Delay or Set False Path constraints. As a result, when you use the Write Script command after Replace FPGA, Write Script does not include in the DC file it creates any Set Max Delay or Set False Path constraints applied before the Replace FPGA. To include these constraints in the DC file, you must re-apply them after you use the Replace FPGA command. Also, you must use the full hierarchical names with the Set Max Delay and Set False Path commands.

The VHDL Set Max Delay and Set False Path example follows.

analyze -f vhdl file1.vhd analyze -f vhdl file2.vhd . . elaborate TOPLVLENTITY set_port_is_pad “*” insert_pads /* Set Timing Constraints */ create_clock... set_max_delay... set_false_path... set_input_delay... set_output_delay... compile replace_fpga ungroup -all -flatten / *Reapply Timing Constraints */ report_port all_clocks all_registers set_max_delay... set_false_path... write_script > “top.dc” sh dc2ncf “top.dc” exit

The Verilog Set Max Delay and Set False Path example follows.

read -f verilog file1.v read -f verilog file2.v . . read -f verilog filen.v set_port_is_pad “*” insert_pads /* Set Timing Constraints */ create_clock... set_max_delay set_false_path compile replace_fpga ungroup -all -flatten /* Reapply Timing Constraints */ report_port all_clocks all_registers set_max_delay... set_false_path... write_script > “top.dc” sh dc2ncf “top.dc” exit

Set Multicycle Path

DC2NCF does not support translation of the Set Multicycle Path command. However, you can achieve equivalent functionality with the Set Max Delay command. These two constraints differ in the interpretation of their numerical field.

The syntax of the two commands follows.

set_multicycle_path path_multiplier,[-rise | -fall] \ [-setup | -hold] [-start | -end] \ [-from from_list] [-to to_list] [-reset_path]

set_max_delay delay_value [-rise | -fall] \ [-from from_list] [-to to_list] \ [-group_path group_name] [-reset_path]

Delay_value specifies the absolute delay value in nanoseconds for the path between the indicated start and end points. The period of the clock that controls the path between the indicated start and end points multiplies path_multiplier and specifies the path delay.

You can use the Set Max Delay command instead of the Set Multicycle Path command by using the clock period multiplied by the path_multiplier for the delay_value. The following example illustrates this command substitution.

create_clock my_clock_port -period 50

set_multicycle_path 2 -from find(cell,“a_reg”) \ -to find(cell,“b_reg”)

Alternatively, you can express this as shown in the following example.

create_clock my_clock_port -period 50

set_max_delay 100 -from find(cell,“a_reg”) \ -to find(cell,“b_reg”)

NOTE

When DC2NCF translates Synopsys timing commands into Xilinx syntax, point-to-point exception commands (such as Set Max Delay and Set False Path) result in timegroup statements in the resulting NCF file. For identification purposes, the names allocated to timegroups include the line number of the related command in the Synopsys script file. The following example shows the translation of a line of a Synopsys script file.

set_max_delay 57 -from find(clock,clocka)

The DC2NCF output NCF file appears as follows.

TIMEGROUP tg_5_dest = FFS:LATCHES:RAMS:PADS;

ts_01 = FROM:clocka:TO:tg_5_dest:57;