After you insert the I/O pads, you can optimize your design for area, speed, or a combination of both. To get the most effective results from FPGA Compiler, apply accurate and achievable constraints. For example, if you set a timing goal of 0 ns on all ports, FPGA Compiler attempts to meet this goal by duplicating logic to reduce critical paths. This can result in a significant and possibly unwarranted increase in CLB and interconnect usage.
The following sections describe the commands you use to compile and optimize your HDL design.
CLBs contain Boolean logic implemented in both function generators and flip-flops. Compiling a hierarchical design or a design that uses a DesignWare module does not optimize the logic across the hierarchical boundary because DesignWare modules exist inside their own hierarchical boundaries. Therefore, some CLBs only implement flip-flops and contain unused function generators and other CLBs only implement function generators and contain unused flip-flops. Additionally, the Boolean logic in one hierarchy is not optimized with that in another to reduce the CLB area or logic levels.
The choice of hierarchical boundaries can have a significant impact on the area and speed of the synthesized design. Using FPGA Compiler, you can optimize a design while preserving these hierarchical boundaries.
The TOP design, illustrated in the following figure, references two sub-blocks, one completely combinatorial (block1) and one completely sequential (block2).
Figure 3.8 Sequential and Combinatorial Design |  |
FPGA Compiler cannot move logic across levels of hierarchy. To maintain the hierarchy you need two CLBs to implement the TOP design. FPGA Compiler uses one CLB to implement the OR gate and another to implement the FDC flip-flop.
However, if FPGA Compiler merges two subdesigns into a single level of hierarchy, you need only one CLB to implement the TOP design, illustrated in the following figure. FPGA Compiler can merge the combinatorial and sequential logic into one CLB.
Figure 3.9 Merging into a Single Level of Hierarchy | |
To check if FPGA Compiler can combine the combinatorial and sequential logic across hierarchical boundaries, optimize the design with and without hierarchy, and then compare the results as described in the following sections.
By default, FPGA Compiler does not flatten your design hierarchy. You must use the Compile command with the Ungroup All option to flatten your design. However, FPGA Compiler only partially optimizes logic across hierarchical modules. Full optimization is possible across those parts of your design hierarchy ungrouped in FPGA Compiler. Flatten or reconstruct hierarchy artificially prior to using the Compile command by issuing the Group and Ungroup commands. Follow the guidelines for controlling flattening in the Synopsys Design Compiler Family Reference Manual.
Flattening eliminates the existing logic structure. In general, you can flatten random control logic because automatic structuring usually improves upon manual structuring. For FPGA designs, flatten designs when the number of CLBs needed to implement a Boolean function seems too high or there are too many logic levels. You probably do not need to flatten regular or highly structured designs such as adders and ALUs designed with an explicit structure.
Flattening works especially well for the FPGA CLB structure because FPGA Compiler has a built-in optimizer for Boolean logic. This algorithm works efficiently when the structure decomposes sufficiently so that the Boolean logic can map into the CLB function generators.
To compile the design and maintain its hierarchy, enter the following command.
compile -map_effort [low|med|high] \
-boundary_optimization
This command enables some logic optimization to occur across hierarchical boundaries. For more information on this option, refer to the Synopsys Design Compiler Family Reference Manual.
Even a flat design can end up containing hierarchical blocks after compiling. These hierarchical blocks contain either Synopsys DesignWare modules or XDW modules mapped during the optimization process.
To compile the design without hierarchy, enter the following command.
compile -map_effort [low|med|high] -ungroup_all
This command creates a flattened design and then optimizes it.
If your design contains Synopsys DesignWare modules (after the first compile), re-compile your design using the Ungroup All option. This command does not optimize XDW modules but instead optimizes the entirely combinatorial Synopsys DesignWare modules. You cannot optimize XDW modules because FPGA Compiler interprets them as “black boxes.” The CLBs that implement the XDW parts have unused flip-flops but the Xilinx design implementation tools can correct this later on in the implementation flow.
Using the Ungroup command with the All Flatten option and then compiling differs substantially from invoking the Compile command with the Ungroup All option. If you run the Ungroup command before the using the Compile command, DesignWare components inferred during compilation retain their hierarchy and can cause the usage of unnecessary CLBs. See your Synopsys documentation for more information on the Ungroup command.
This section describes the design flow if your design contains instantiated I/O cells. If you instantiate all I/O buffers (FPGA Compiler does not need to automatically insert I/O buffers), do not use the Set Port Is Pad and Insert Pads commands. Place a Dont Touch attribute on all instantiated I/O buffers.
If your design contains some instantiated I/O buffers and you want FPGA Complier to automatically insert the rest of the I/O buffers, do the following.
See the bidi_reg.vhd and bidi_reg.v examples in the “Inserting Bidirectional I/Os” section for designs that contain both instantiated I/Os and I/Os inserted using FPGA Compiler. The bidi_reg.script (VHDL) in the provides an example script file illustrating the correct design flow.
The following sample script file demonstrates how to compile your XC4000E/L/EX/XL/XLA/XV designs using FPGA Compiler.
/* ==================================================*/
