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Using the Global Set/Reset Net

All Xilinx FPGA devices have a dedicated Global Set/Reset (GSR) net that initializes all CLBs and IOB flip-flops. The function of the GSR net is separate from and overrides the individual flip-flop or latch Preset (PRE) and Direct Clear (CLR) pins.

If your design includes a signal used to globally initialize all the flip-flops or latches, use the GSR net to increase design performance by reducing the overall routing congestion. The GSR net, a dedicated routing resource, exists outside of the general purpose interconnect. You can disconnect your design's global initialization signal from the flip-flops and latches in your design and implement this function using the device's dedicated GSR net.

Figure 3.6 Emulation of Power-on State “1” with Inverters (XC3000A/L, XC3100A, and XC5200)

Accessing Global Set/Reset Using STARTBUF

Access an FPGA's GSR signal by attaching a net to the input pin on the STARTBUF cell. Asserting the net attached to the STARTBUF block's GSR pin also asserts FPGA Global Set/Reset causing every flip-flop and latch in the device to assume its power-on state.

You must instantiate the STARTBUF block.

The GSR net does not appear in the pre-placed and routed netlist. Asserting the GSR signal to High (the default) sets every flip-flop and latch to the same state it had at the end of configuration, illustrated in the following tables. When you simulate the placed and routed design, the simulator's translation program correctly inserts the functionality.

Any signal can drive the STARTUP block's GSR pin, however, do not use flip-flop or latch output signals.

Synthesizing/Simulating for VHDL Global Set/Reset Emulation

VHDL requires a testbench to control all signal ports. You can instantiate certain VHDL-specific components, explained in the following sections, in the RTL and post-synthesis VHDL description to allow the simulation of the global signals for global set/reset and global 3-state.

NGD2VHDL creates a port in your back-annotated design entity for stimulating the global set/reset or 3-state enable signals. This port does not actually exist on the configured part.

When running NGD2VHDL, you do not need to use the -gp switch to create an external port if you instantiate a STARTUP block in your implemented design. The port is already identified and connected to the global set/reset or 3-state enable signal. If you do not use the -gp option or a STARTBUF block, you must use special components, as described in the following sections.

Using STARTBUF in VHDL

STARTBUF replaces STARTUP. With STARTBUF you can functionally simulate the GSR/GR net in both function and timing simulation. By connecting the input pin of the STARTBUF to a top-level port and using STARTBUF as the source for all asynchronous set/reset signals in a design, Xilinx M1 software can automatically optimize the design to use the GSR/GR. Because you can use STARTBUF in functional simulation (unlike STARTUP), when you use STARTBUF you can map to the GSR/GR in a device. You can still use STARTUP, but it does not always provide correct GSR/GR in HDL flows.

The STARTBUF component passes a reset or 3-state signal in the same way that a buffer allows simulation to proceed and also instantiates the STARTUP block for implementation. One version of STARTBUF works for all devices, however, the XC5200 and the XC4000 STARTUP blocks have different pin names. Implementation with the correct STARTUP block occurs automatically. The following shows an instantiation example of the STARTBUF component.

U1: STARTBUF port map (GSRIN => DEV_GSR_PORT, GTSIN =>DEV_GTS_PORT, CLKIN => `0', GSROUT => GSR_NET, GTSOUT => GTS_NET, Q2OUT => open, Q3OUT => open, Q1Q4OUT => open, DONEINOUT => open):

You can use one or both of the input ports (GSRIN and GTSIN) of the STARTBUF component and the associated output ports (GSROUT and GTSOUT). You can use pins left “open” to pass configuration instructions to the implementation tools by connecting the appropriate signal to the port instead of leaving it open.

Instantiating a STARTUP Block in VHDL

The STARTUP block traditionally instantiates to identify the GR, PRLD, or GSR signals for implementation. However, simulation can occur only when the net attached to the GSR or GTS goes off the chip because the STARTUP block does not have a simulation model. You can use the new components described below to simulate global set/reset or 3-state nets whether or not the signal goes off the chip.

Setting Direct Preset or Direct Clear

You can program each flip-flop and latch as either Preset or Clear but not both. The device's automatic assertion of its own GSR net asynchronously sets flip-flops and latches as either Preset or Cleared upon completion of configuration. Use individual flip-flop and latch Preset (PRE) and Clear (CLR) pins to set them as preset or cleared.

The power-on state of a register or latch and the selection of PRE or CLR pin must match. For example, a register with a CLR pin assumes the value of `0' on power-up. Alternatively, a register with a power-up state of `0' can only have a CLR pin.

To get an asynch set or async reset FF, describe the behavior in the RTL code. If you only want to describe the power-on state of an FF, connect the async set or async reset signal of the RTL FF to the ROCBUF.

Increasing Performance with the GSR Net

Many designs have a net that initializes the majority of the design's flip-flops. If this signal initializes all the design's flip-flops, you can use the GSR net.

To have your HDL simulation match that of the resulting design, modify your HDL code so that asserting the GSR signal presets or clears every flip-flop and latch. You must ensure that this signal does not get routed around general purpose interconnect but instead uses the dedicated global routing resource. Disconnect this signal with the Disconnect Net command after you compile your design but before you save it.

Alternatively, the Xilinx tools move this signal on to the device's dedicated GSR routing network when the following conditions apply.

The following figure illustrates this flow.

Figure 3.7 Increasing Performance with GSR Net

The following VHDL and Verilog examples illustrate a design that uses the GSR net. The design contains two flip-flops, one reset and one set when the signal “RST” is High.

The following example shows VHDL code before using the GSR net.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity gsr_ex is
port ( CLK,RST : in STD_LOGIC;
ST: buffer std_logic_vector (1 downto 0));
end gsr_ex;

architecture EXAMPLE of gsr_ex is

begin
process (CLK, RST)
begin
if RST= `1' then
ST <= “01”;
elsif (CLK'event and CLK= `1') then
ST <= ST + “01”;
end if;
end process;

end EXAMPLE;

The following example shows Verilog code before using the GSR net.

module gsr_ex (CLK, RST, ST) ;
input CLK ;
input RST ;
output [1:0] ST;

reg [1:0] ST;

always @(posedge CLK or posedge RST)
begin
if (RST == 1'b1)
ST = 2'b01 ;
else
ST = ST + 1'b1 ;
end

endmodule

Add the reset signal in your design to the GSR pin of the STARTUP block. This makes the Xilinx tools move this signal on to the dedicated routing network if all other conditions are satisfied.

To utilize the GSR net, add the STARTUP block to your design by instantiation, illustrated in the following examples. The following example shows VHDL code using the GSR net.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity top_gsr is
port ( CLK,GSR_top,RST : in STD_LOGIC;
ST: buffer STD_LOGIC_VECTOR (1 downto 0));
end top_gsr;

architecture EXAMPLE of top_gsr is
component STARTUP
port ( GSR: in STD_LOGIC);
end component;

component gsr_ex
port ( CLK,RST: in STD_LOGIC;
ST : buffer STD_LOGIC_VECTOR (1 downto 0));
end component;

begin

U1 : STARTUP port map (GSR=>GSR_top);
U2 : gsr_ex port map (CLK=>CLK,RST=>RST,ST=>ST);
end EXAMPLE;

The following example shows Verilog code using the GSR net.

module top_gsr (CLK, GSR_top, RST, ST) ;
input CLK ;
input GSR_top;
input RST ;
output [1:0] ST;

STARTUP U1 (.GSR(GSR_top)) ;
gsr_ex U2 (.CLK(CLK), .RST(RST), .ST(ST)) ;

endmodule

Because the STARTUP block does not use any outputs in this example, FPGA Compiler removes the STARTUP block unless you specify the Dont Touch attribute for U1. You must issue this command before inserting the I/O pads.

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