Using Supplied Libraries Descriptions

This section describes the Xilinx-supplied libraries and supported part types and speed grades. The “Library Descriptions” table contains the following variables.

family - refers to the family of Xilinx devices, for example, 4000e, 4000ex, or 3000a.
parttype - the specific Xilinx device, for example, 4003e, 4005e, or 3120a.
4kparttype - the specific Xilinx XC4000 device, for example, 4003e or 4005e.
-s - indicates the part type's speed grade, for example, -5. Not all speed grades are available for all part types. Run Synlibs with the -h option to get a listing of all available part type and speed grade combinations.

Table 6_3 Library Descriptions

Library	Description	FPGA Compiler or Design Compiler
xgen_3000a.db	The xgen_3000a.db library describes the XC3000a cells that do not contain timing information, for example, CLBMAP, PULLUP, net flags, and VCC.	Both
xgen_3000l.db	The xgen_3000l.db library describes the XC3000l cells that do not contain timing information, for example, CLBMAP, PULLUP, net flags, and VCC.	Both
xgen_3100l.db	The xgen_3100l.db library describes the XC3100l cells that do not contain timing information, for example, CLBMAP, PULLUP, net flags, and VCC.	Both
xgen_4000e.db	The xgen_4000e.db library describes the XC4000e cells that do not contain timing information, for example, FMAP, PULLUP, and VCC.	Both
xgen_4000l.db	The xgen_4000l.db library describes the XC4000l cells that do not contain timing information, for example, FMAP, PULLUP, and VCC.	Both
xgen_4000ex.db	The xgen_4000ex.db library describes the XC4000ex cells that do not contain timing information, for example, FMAP, PULLUP, and VCC.	Both
xgen_4000xl.db	The xgen_4000xl.db library describes the XC4000xl cells that do not contain timing information, for example, FMAP, PULLUP, and VCC.	Both
xgen_4000xla.db	The xgen_4000xla.db library describes the XC4000xla cells that do not contain timing information, for example, FMAP, PULLUP, and VCC.	Both
xgen_4000xv.db	The xgen_4000xv.db library describes the XC4000xv cells that do not contain timing information, for example, FMAP, PULLUP, and VCC.	Both
xgen_5200.db	The xgen_5200.db library describes the XC5200 cells that do not contain timing information, for example, FMAP, PULLUP, and VCC.	Both
xprim_family-s.db	The xprim_family-s.db libraries describe the Xilinx XC4000E/L/EX/XL/XLA/XV, XC3000A/L, XC3100A/L, and XC5200 gates, flip-flops, input/output buffers, and other simple circuit elements whose delays do not vary with the density of the part. These files contain worst-case commercial (WCCOM) timing information.	Both
xprim_parttype-s.db	The xprim_ parttype-s.db libraries describe the Xilinx XC4000E/L/EX/XL/XLA/XV, XC3000A/L, XC3100A/L, and XC5200 3-state buffers, clock buffers, I/O decoders, and other simple circuit elements whose delays vary with the density of the part. These files contain WCCOM timing information.	Both
xio_4kparttype-s.db	The xio_4kparttype-s.db libraries describe the Xilinx XC4000E/L/EX/XL/XLA/XV input/output buffers whose delays vary with the device type. These files contain WCCOM timing information.	Both
xio_5kparttype-s.db	The xio_5kparttype-s.db libraries describe the Xilinx XC5200 input/output buffers whose delays vary with the device type. These files contain WCCOM timing information.	Both
xfpga_family-s.db	The xfpga_family-s.db libraries describe the Xilinx XC4000E/L/EX/XL/XLA/XV, XC3000A/L, XC3100A/L, and XC5200 CLB and IOB primitives, which allow the FPGA Compiler to directly map to CLBs and IOBs. These files contain WCCOM timing information.	FPGA Compiler
xdc_family-s.db	The xdc_ family-s.db libraries contain Boolean functions to which the Synopsys tools map.	Design Compiler
xdw_4000e.sldb	The xdw_4000e.sldb library contains the DesignWare macros that allow adders, subtracters, incrementers, decrementers, and comparators to map directly to Xilinx DesignWare modules.	Both
xdw_4000l.sldb	The xdw_4000l.sldb library contains the DesignWare macros that allow adders, subtracters, incrementers, decrementers, and comparators to map directly to Xilinx DesignWare modules.	Both
xdw_4000ex.sldb	The xdw_4000ex.sldb library contains the DesignWare macros that allow adders, subtracters, incrementers, decrementers, and comparators to map directly to Xilinx DesignWare modules.	Both
xdw_4000xl.sldb	The xdw_4000xl.sldb library contains the DesignWare macros that allow adders, subtracters, incrementers, decrementers, and comparators to map directly to Xilinx DesignWare modules.	Both
xdw_4000xla.sldb	The xdw_4000xla.sldb library contains the DesignWare macros that allow adders, subtracters, incrementers, decrementers, and comparators to map directly to Xilinx DesignWare modules.	Both
xdw_4000xv.sldb	The xdw_4000xv.sldb library contains the DesignWare macros that allow adders, subtracters, incrementers, decrementers, and comparators to map directly to Xilinx DesignWare modules.	Both
xdw_5200.sldb	The xdw_5200.sldb library contains the DesignWare macros that allow adders, subtracters, incrementers, decrementers, and comparators to map directly to Xilinx DesignWare modules.	Both
xprim_family/*.ngl	Data files containing XSI library component expansion for NGDBuild.	Both

Finding Supported Part Types and Speed Grades

Run Synlibs with the -h option to get a listing of all available part type and speed grade combinations. You can also refer to the Xilinx online Data Book at http://www.xilinx.com for current speed grade information.

Finding Unsupported Part Types and Speed Grades

If designing for a part type or speed grade for which no libraries are available, use the libraries for the closest part type or speed grade in the same family. Indicate the part type or speed grade actually used when you run PAR. The timing constraints in the NCF file can need adjustment.

NOTE

For more information on specifying the part type, refer to the Development System Reference Guide.