Installing the Software

You must have the following versions of software to use this tutorial.

• Synopsys FPGA Compiler Version 3.4b or later or the Synopsys Design Compiler Version 3.4b or later
  
  
• XSI Version M1
  
  
• Xilinx Development System Version M1
  
  

Before Beginning the Tutorial

Before you begin this tutorial, set up your workstation to use Synopsys FPGA Compiler or Design Compiler and the Xilinx software as follows.

1. Verify proper configuration of your system. Consult the release notes and installation notes that came with your software package for more information.
   
   
2. Install the following sets of software.
   
   
   • Xilinx Development System
     
     
   • XSI software
     
     
   • Synopsys FPGA Compiler or Design Compiler version 3.4b or later
     
     
   • Synopsys VSS-VITAL version 3.4b or later
     
     
3. Verify the installation. When you finish the installation, verify that your .cshrc or setup file contains lines similar to the following.
   
   

NOTE

$XILINX is the directory for all Xilinx software. $SYNOPSYS is the directory for the Synopsys software.

setenv XILINX location_of_Xilinx_software
setenv SYNOPSYS location_of_Synopsys_software
set path=($SYNOPSYS/sparc/syn/bin \
$SYNOPSYS/sparc/sim/bin \
$XILINX/bin/sun $path)

Understanding the Tutorial Design

The Calc design is a 4-bit processor with a stack. The processor performs functions between an internal register and either the top of the stack or data input from external switches. Calc stores the results of various operations in the register and displays them in hexadecimal on a seven-segment display. The top value in the stack displays in binary on a bar LED. A count of the items in the stack displays as a “gauge” on another bar LED.

Calc consists of the following functional blocks.

• ALU - this block performs arithmetic functions of the processor.
  
  
• CONTROL - this module decodes the opcodes into control lines for the stack and ALU.
  
  
• STACK - the stack is a four-nibble storage device implemented using synchronous RAM in the XC4000 design. You can substitute the RAM4_9K module, which uses flip-flops, in place of the RAM16X4S macro in the STACK schematic to implement the stack in designs for devices other than XC4000.
  
  
• DEBOUNCE - this circuit debounces the “execute” switch, providing a one-shot output.
  
  
• SEG7DEC - this block decodes the output of the ALU for display on the 7-segment decoder.
  
  
• CLOCKGEN - uses an internal oscillator circuit in XC4000 devices to generate the clock signal.
  
  
• BARDEC - uses a “gauge” consisting of four LEDs to show how many items are on the stack.
  
  
• SWITCH7 - this user-defined module, consisting of seven input flip-flops, latches the switch data.
  
  

Installing the Tutorial

The tutorial files install automatically when you install the Xilinx software.

You can find the FPGA Compiler tutorial files in the following directory.

$XILINX/synopsys/tutorial/fpga

You can find the Design Compiler tutorial files in the following directory.

$XILINX/synopsys/tutorial/dc

The following sections provide a description of the tutorial files.

VHDL Design Files

Calc.vhd is the top level design file but it also includes the following lower-level VHDL modules.

• alu.vhd
  
  
• bardec.vhd
  
  
• clockgen.vhd
  
  
• control.vhd
  
  
• count3.vhd
  
  
• debounce.vhd
  
  
• seg7dec.vhd
  
  
• stack.vhd
  
  
• statmach.vhd
  
  
• switch7.vhd
  
  

VHDL Testbench

You can find the testbench.vhd file in this directory. You can use the same testbench to perform both RTL and timing simulation.

Script Files

The following four script files automate the steps in this tutorial.

• behv_sim.csh
  
  
• synthesize.csh
  
  
• implement.csh
  
  
• tim_sim.csh
  
  

NOTE

When you run synthesize.csh, FPGA Compiler or Design Compiler executes calc.script, a dc_shell synthesis script file.

Setup Files

The following two setup files are provided.

• .synopsys_dc.setup
  
  
• .synopsys_vss.setup
  
  

Models for RTL Simulation

The following RTL simulation files are included.

• buf.vhd
  
  
• bufg.vhd
  
  
• osc4.vhd
  
  
• ram16x1s.vhd
  
  

Readme File

The Readme file provides the steps you need to follow to complete the tutorial.

Copying the Tutorial Files

To copy the tutorial files, follow these steps.

1. Create a project directory that you can write to when using the tutorial, as shown in the following examples.
   
   mkdir calc_4kex
   
   
2. Copy the tutorial files from $XILINX/synopsys/tutorial/fpga (FPGA Compiler tutorial).
   
   cp -r $XILINX/synopsys/tutorial/fpga calc_4kex
   cd calc_4kex/fpga/vhdl
   mkdir WORK
   
   Or copy the files from $XILINX/synopsys/tutorial/dc (Design Compiler tutorial) into the appropriate project directory.
   
   cp -r $XILINX/synopsys/tutorial/dc calc_4kex
   cd calc_4kex/dc/vhdl
   mkdir WORK