Before you start the tutorial, check your environment settings as follows.
Check that the path settings point to the required Synopsys and Xilinx software. If either of these environment variables is incorrectly set, correct them before continuing with the tutorial.
With these environment settings in place, the .synopsys_dc.setup file and the .synospys_vss.setup file point to the location of the synthesis libraries and the simulation libraries, respectively.
Look at the VHDL description of the Calc design in calc.vhd. Notice the instantiation of the lower level modules, as well as other Xilinx primitives.
The Startup block, one of the primitives instantiated in the calc.vhd file, allows the use of dedicated resources on the chip to set or reset all flip-flops and I/O latches on the device. The GSR net performs the sets or resets. Access the GSR net from the GSR pin on the Startup Block.
Using the GSR net via the Startup block enhances design performance by greatly reducing fanout and routing congestion. The Calc design uses an internal reset signal called GBLRESET, obtained by inverting the signal applied to the NOTGBLRESET port. GLBRESET, generated by inverting NOTGBLRESET, is also connected to the GSR input pin of the Startup block. This results in the NOTGBLRESET pin becoming the global reset/set pin for the entire FPGA.
Because the GSR net has dedicated routing resources that connect to the Preset or Clear pin of the flip flops, you do not need to use general purpose routing resources to connect to these pins. In the Calc design, the signal called GBLRESET initializes every flip flop used in the design.
The following example shows relevant segments of calc.vhd that display this feature.
entity calc is
Use VSS version 3.4b or later to perform a functional simulation on the tutorial design. To properly analyze and simulate XC4000E/EX/XV designs using VSS, your working directory must have a .synopsys_vss.setup file. The tutorial directory contains a .synopsys_vss.setup file.
When simulating, you must analyze the design's modules according to hierarchical precedence, starting with the lowest. Analyze the RTL models for all instantiated primitives, followed by the design files, with the Synopsys VHDLAN command.
To simulate the design, perform the following steps.
vhdlan bufg.vhd
vhdlan osc4.vhd
vhdlan ram16x1s.vhd vhdlan clockgen.vhd
vhdlan count3.vhd
vhdlan statmach.vhd
vhdlan stack.vhd
vhdlan bardec.vhd
vhdlan seg7dec.vhd
vhdlan alu.vhd
vhdlan control.vhd
vhdlan switch7.vhd
vhdlan debounce.vhd
vhdlan calc.vhd vhdlan testbench.vhdDuring simulation, the testbench applies stimulus to the design, and monitors and records its outputs. For this tutorial, the testbench applies stimulus to the Calc design by reading information from a text file called stimulus.txt, and writes the design's responses to a text file called results.txt.
The stimulus file allows you to enter simulation test-vectors on the Calc design in the form of Xilinx Demonstration Board switch settings (you can apply these are same switch settings to the Demonstration Board). The first few lines of the example stimulus.txt file follow.
01100011
The testbench monitors the design's outputs and interprets them in the same fashion as the Xilinx Demonstration Board. The results of the simulation convert to a text file that depicts the state of the LED indicators and seven segment display on the Xilinx Demonstration Board. The results.txt file stores the results, as shown in the following figure.
Figure 7.1 Results.txt File |  |
You can provide your own stimulus by editing the stimulus.txt file. The following table provides valid operations and functions.
| 2 | 3 | 4 | 5 | 6 | 7 | 8 | Operation |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | DATA | Add between switches and register | |||
| 0 | 0 | 1 | DATA | AND between switches and register | |||
| 0 | 1 | 0 | DATA | OR between switches and register | |||
| 0 | 1 | 1 | DATA | XOR between switches and register | |||
| 1 | 0 | 0 | DATA | Subtract switch value from register | |||
| 1 | 0 | 1 | X | X | X | X | Clear register |
| 1 | 1 | 0 | DATA | Load register | |||
| 1 | 1 | 1 | 0 | 0 | 0 | X | Add between stack and register |
| 1 | 1 | 1 | 0 | 0 | 1 | X | AND between stack and register |
| 1 | 1 | 1 | 0 | 1 | 0 | X | OR between stack and register |
| 1 | 1 | 1 | 0 | 1 | 1 | X | XOR between stack and register |
| 1 | 1 | 1 | 1 | 0 | 0 | X | Subtract stack value from register |
| 1 | 1 | 1 | 1 | 0 | 1 | X | Push register value to stack |
| 1 | 1 | 1 | 1 | 1 | 0 | X | Pop stack value to register |
| 1 | 1 | 1 | 1 | 1 | 1 | X | NOP |
Bit 1 is the signal used to clock the instruction in to the calculator.
The testbench terminates the simulation by executing an instruction that generates a false assertion. This stops an otherwise open-ended simulation. The simulation stops only once when the last line of the stimulus file reads. The simulation ends with the following message.
Assertion ERROR at 1500200.0 NS in design unit TESTBENCH(TUTORIAL) from process /TESTBENCH/STIMULUS:
“Stop the simulation!”
This message indicates that the last line of stimulus.txt has read and the file results.txt now contains information.
You can quit the VSS Debugger now and look at the results in the file results.txt.
You can now synthesize the design with the following command.
source synthesize.csh
While the synthesize.csh executes, look at the file. Synthesize.csh is a script file that invokes the Synopsys dc_shell and executes the script file called calc.script. The transcript of the synthesis session stores in a log file called calc_synth.log. The following command in synthesize.csh accomplishes the entire process.
dc_shell -f calc.script | tee calc_synth.log
The script file shown here is for FPGA Compiler. For Design Compiler, refer to the calc.script file in your Design Compiler tutorial directory.
The calc.script reproduced here contains step-by-step explanations.
/*================================================= */
TOP = calc
MOD1 = clockgen
MOD2 = count3
MOD3 = statmach
MOD4 = stack
MOD5 = bardec
MOD6 = seg7dec
MOD7 = alu
MOD8 = control
MOD9 = switch7
MOD10 = debounce
designer = “XSI Team”
company = “Xilinx, Inc” /* ================================================= */
/* Analyze and Elaborate the design file and specify */
/* the design file format. */
/* ================================================= */
analyze -format vhdl MOD1 + “.vhd”
analyze -format vhdl MOD2 + “.vhd”
analyze -format vhdl MOD3 + “.vhd”
analyze -format vhdl MOD4 + “.vhd”
analyze -format vhdl MOD5 + “.vhd”
analyze -format vhdl MOD6 + “.vhd”
analyze -format vhdl MOD7 + “.vhd”
analyze -format vhdl MOD8 + “.vhd”
analyze -format vhdl MOD9 + “.vhd”
analyze -format vhdl MOD10 + “.vhd”
analyze -format vhdl TOP + “.vhd”
elaborate TOP
/* ================================================= */
/* Set the current design to the top level. */
/* ================================================= */
current_design TOP
/* ================================================= */
/* Set the synthesis design constraints. */
/* ================================================= */
remove_constraint -all /* ================================================= */
/* Apply dont_touch attributes to instantiated prims */
/* ================================================= */
dont_touch STARTUPBLK
dont_touch “OSCILLATOR/OSCILLATOR”
dont_touch “OSCILLATOR/CLOCK_BUF”
/* ================================================= */
/* Indicate those ports on the top-level module that */
/* should become chip-level I/O pads. Assign any I/O */
/* attributes or parameters and perform the I/O */
/* synthesis. */
/* ================================================= */
set_port_is_pad “*”
set_pad_type -slewrate HIGH all_outputs()
insert_pads
/* ================================================= */
/* Synthesize and optimize the design */
/* ================================================= */
compile -boundary_optimization /* ================================================= */
/* Write the design report files. */
/* ================================================= */
report_fpga > TOP + “.fpga”
report_timing > TOP + “.timing”
/* ================================================= */
/* Write out the design to a DB file. (Post compile) */
/* ================================================= */
write -format db -hierarchy -output TOP + “_compiled.db”
/* ================================================= */
/* Replace CLBs and IOBs with gates. */
/* ================================================= */
replace_fpga
/* ================================================= */
/* Set the part type. */
/* ================================================= */
set_attribute TOP “part” -type string “4028expg299-3”
/* ================================================= */
/* Write out the design to a DB. (Post replace_fpga) */
/* ================================================= */
write -format db -hierarchy -output TOP + “.db”
/* ================================================= */
/* Flatten the design's hierarchy to rationalize */
/* netlist and constraints files */
/* ================================================= */
ungroup -all -flatten
/* ================================================= */
/* Save design in XNF format as <design>.sxnf */
/* ================================================= */
write -format xnf -hierarchy -output TOP + “.sxnf”
/* ================================================= */
/* Write-out the timing constraints that were */
/* applied earlier. */
/* ================================================= */
write_script > TOP + “.dc”
/* ================================================= */
/* Call the Synopsys-to-Xilinx constraints translator */
/* utility DC2NCF to convert the Synopsys constraints */
/* to a Xilinx NCF file. You may want to view */
/* dc2ncf.log to review the translation process. */
/* ================================================= */
sh dc2ncf TOP + “.dc”
/* ================================================= */
/* Exit the Compiler. */
/* ================================================= */
exit
/* ================================================= */
/* Now run the Xilinx design implementation tools. */
/* ================================================= */ Figure 7.2 Design Analyzer Window | |
Read.Synthesis creates a netlist and constraints file in the project directory. The design implementation tools read both of these files, which convey information about the functionality of the design. This functionality information includes how to allocate logic to FPGA function generators, timing goals that drive the place and route process, and how to allow the Xilinx static timing analyzer, TRACE, to report any timing violations.
The script implement.csh runs the automatic design implementation tools. Run this script by entering the following command.
source implement.csh
Implement.csh invokes the netlist translator, NGDBuild, which translates the Synopsys generated netlist (calc.sxnf) to a Xilinx netlist (calc.ngd). It then invokes the mapper, MAP, which allocates the logic to CLBs and IOBs. Finally, it invokes the place and route program, PAR. PAR takes a mapped design, calc.ncd, as its input and produces a placed and routed design. Specify the file name with the -w switch. For the tutorial design, the routed version is calc_routed.ncd.
Look at the report files produced by MAP, calc.mrp, and PAR, calc_routed.par and calc_routed.pad (the latter indicates pins used for the I/Os).
At this point, you can now run the bitstream generation program, BitGen, to create configuration data for the physical device, or view the place and route results with EPIC, a low-level design editor.
After placing and routing Calc, you can perform a timing simulation with the VITAL simulator as follows.
source tim_sim.csh
Look at tim_sim.csh.
The same testbench used to perform an RTL simulation, testbench.vhd, also performs a timing simulation.
Running NGDANNO back-annotates calc_routed.ncd, the results of the place and route process. NGDANNO takes as its inputs the routed design file, calc_routed.ncd, and the source file, calc.ngm. Invoke NGD2VHDL on the routed and back-annotated design file to produce a structural, VITAL compliant, VHDL model for the entire design, calc_routed.vhd. NGD2VHDL also produces an SDF file, called calc_routed.sdf, that carries all the delays associated with the placed and routed design.
As before, when you performed an RTL simulation, you must analyze the design files in hierarchical order. Analyze calc_routed.vhd first and then the testbench, testbench.vhd.
The file called stimulus.txt provides the stimulus, storing the results of the simulation in results.txt. You can copy the results.txt file generated during the earlier RTL simulation to compare with the results you next generate.
The VHDL Simulator launches and reads in the testbench, the back-annotated VHDL model for the placed and routed design, and the associated SDF file. Start the simulation by pressing the “RUN” button or entering the Run command at the command line.
