New Features

These are the major new features supported for this release.

• New FPGA and CPLD families in the release (XC4000XLA, XC9500XL, SpartanXL, and Virtex)
  
  
• Fully integrated design environment with automated design processing
  
  The Foundation Series Project Manager is the first design environment which integrates the Xilinx implementation tools. Furthermore, the HDL project management capabilities provided as part of Synopsys' FPGA Express are seamlessly integrated into the Foundation Series "Unified Project Manager." This embedding of the industry's most powerful FPGA design tools provides dramatic improvements in the project management revision control capabilities. The new Foundation Series design flows also feature powerful, push-button compilation without sacrificing design performance or runtime.
  
  
• New synthesis technology
  
  The Foundation Series Base Express and Foundation Express product configurations both feature HDL synthesis from Synopsys FPGA Express. This release of the Foundation Series enables true HDL design flows as well as mixed-language (VHDL and Verilog HDL) synthesis and optimization. Support for mixed-language design flows is becoming increasingly important as the use of third party or inter-organizational Intellectual Property (IP or cores) grows. Check out the “Foundation Express” section in this chapter to learn more details about the Foundation's synthesis capabilities.
  
  
• New Xilinx Constraints Editor enabling easy system performance specification. The Editor is accessible from the Start button (Start Programs Xilinx Foundation Series Accessories Constraints Editor).
  
  
• JTAG Programmer now supports both CPLDs and FPGAs for download and configuration. Supported families include XC4000E/L/EX/XL/XV/XLA, XC5200, XC9500/XL, and Spartan/XL.
  
  
  
  
• Redefined 1.5 Project Flows: Schematic and HDL
  
  An HDL Flow contains VHDL and Verilog top-level designs with optional black boxes and HDL modules. The entire design is always exported in HDL terms and synthesized.
  
  Any black boxes in the design are passed to the implementation tools for translation. For details, see the “Design Methodologies - HDL Flow” chapter in the Foundation Series User Guide.
  
  A Schematic Flow may only have schematic designs as top-level designs. These top-level designs can contain HDL modules, Finite State Machine macros, and LogiBLOX modules. For details, refer to the “Design Methodologies - Schematic Flow” chapter in the Foundation Series User Guide.
  
  
• Updated CORE Generator^™ System
  
  The Xilinx CORE Generator is an easy-to-use design tool that delivers parameterizable cores, optimized for Xilinx FPGAs. This library includes cores as complex as DSP filters and multipliers, and as simple as delay elements. You can use these cores as building blocks in order to complete your designs more quickly. The cores have been completely tested for compatibility with Foundation 1.5 Software.
  
  The Xilinx CORE Generator CD-ROM is included with your Foundation 1.5 Series Software contents. You will find the CD-ROM in its own case, along with installation instructions on the case cover.
  
  
• New sample designs
  
  bcd_acc - A Verilog-based HDL Flow, this project is a design of a 4-digit BCD accumulator.
  
  calc3ka - This Schematic Flow implements a simple calculator in an XC3020A.
  
  flash - This Schematic Flow contains VHDL and LogiBLOX sub-modules. A free-running counter circuit is targeted to an XC4003 that you can download to the Xilinx demonstration board.
  
  gate - This HDL Flow implements a movement/direction detector in Verilog.
  
  
  hex2bin - This Schematic Flow contains Verilog, LogiBLOX, and CORE Generator sub-modules. It converts Intel hex-formatted data to binary format and stores it into an external 64Kb memory array.
  
  JCT - This collection of designs supports the CPLD-specific JCOUNT tutorial, found in the on-line Foundation Help system.
  
  A Johnson counter is implemented using several design methods: VHDL, ABEL, schematic, schematic with an embedded VHDL macro, and schematic with an embedded ABEL macro.
  
  uart - A top-level ABEL project of a UART receiver that is implemented with XABEL-CPLD synthesis tools.
  
  vtimer4e - An HDL Flow, this project contains a VHDL description of a programmable timer.
  
  watch - This collection of designs is provided for use with the main Foundation tutorial, which can be found in this manual, the Quick Start Guide. A stopwatch is implemented in the two Project Flows: Schematic and HDL. (Both VHDL and Verilog versions are provided for the HDL Flow.)
  
  
• HDL Simulation Capabilities
  
  Foundation Series Software v1.5 now provides the option of adding HDL simulation capabilities to all Foundation design flows. The demand for HDL simulation capabilities has grown as Xilinx provides higher density silicon solutions. To meet this need, Xilinx is shipping an evaluation version of HDL simulators from both Aldec, Incorporated and MTI with this release.
  
  Both of these products may be licensed for evaluation free for up to 30 days. Sale and support for both of these products is provided directly by the vendors.
  
  Active-VHDL product sales are handled directly by Aldec, Inc. and its authorized distributors (email sales@aldec.com).
  
  Customer support is also provided directly by Aldec, Inc. (emailsupport@aldec.com)
  
  You can access the Active-VHDL simulator from the Project Manager (Tools Simulation/Verification ACTIVE-VHDL Behavioral Simulation).
  
  The addition of Active-VHDL to your Foundation Series design environment provides a complete VHDL development environment. This complete development environment includes source code debugging, functional and back-annotated timing simulations, as well as a comprehensive verification methodology based on the use of VHDL testbenches.
  
  All ModelSim product sales are handled directly by MTI and its authorized sales affiliates (email sales@model.com).
  
  Customer support is also provided directly by MTI (email support@model.com or call the main number at (503) 641-1340)
  
  Adding MTI's ModelSim product to the Foundation Series design environment enables simulation of VHDL, Verilog HDL or mixed-HDL designs (Verilog and VHDL). Source code debugging, functional simulation and back-annotated timing simulation are all supported through this integrated solution. The availability of a mixed-language simulation environment offers maximum flexibility to HDL design methodologies which draw on design elements from both Verilog and VHDL.
  
  
• CPLD enhancements
  
  Enhancements in logic optimization and fitting technology have generated faster system clock frequencies, for push-button and timing driven implementations, as well as faster compilation runtimes, averaging 36% improvement.
  
  The XC9500/XL devices are now fully supported in the LogiBLOX module synthesis technology, allowing increased logic utilization for both schematic and HDL-based designs.