Design Description

The design used in this tutorial is a hierarchical, HDL-based design, meaning that the top-level design file is an HDL file that references several other lower-level macros. The lower-level macros are either HDL modules or LogiBLOX modules.

The design begins as an unfinished design. Throughout the tutorial, you complete the design by generating some of the modules from scratch and by completing some others from existing files. When the design is complete, you simulate it to verify the design's functionality.

Watch is a simple runner's stopwatch. There are two external inputs, and three external output buses in the completed design. The system clock is an internally generated signal produced by the OSC4, the internal oscillator in the XC4000 devices. The following list summarizes the input lines and output buses.

Inputs:

• STRTSTOP - Starts and stops the stopwatch. This is an active low signal which acts like the start/stop button on a runner's stopwatch.
  
  
• RESET - Resets the stopwatch to 00.0 after it has been stopped.
  
  

Outputs:

• TENSOUT[6:0] - 7-bit bus which represents the Ten's digit of the stopwatch value. This bus is in 7-segment display format viewable on the 7-segment LED display on the Xilinx demonstration board.
  
  
• ONESOUT[6:0] - Similar to TENSOUT bus above, but represents the One's digit of the stopwatch value.
  
  
• TENTHSOUT[9:0] - 10-bit bus which represents the Tenths' digit of the stopwatch value. This bus is one-hot encoded.
  
  
• GSRT - Active low global reset signal connected to the STARTUP block.
  
  
• EXT_CLK, CLK_SELECT, CLK_OUT_15HZ - Signals required for the hardware verification chapter of this tutorial.
  
  

The completed design consists of the following functional blocks.

• OSC4
  
  Xilinx Unified Library component which represents the XC4000 on-chip oscillator.
  
  
• STATMACH
  
  State Machine module.
  
  
• CNT60
  
  HDL-based module which counts from 0 to 59, decimal. This macro has 2 4-bit outputs, which represent the ones and tens digits of the decimal values, respectively.
  
  
• TENTHS
  
  Logiblox 10-bit, one-hot encoded counter. This macro outputs the tenths digit of the watch value as a 10-bit one-hot encoded value.
  
  
• HEX2LED
  
  HDL-based macro. This macro decodes the ones and tens digit values from hexadecimal to 7-segment display format for viewing on the FPGA Demonstration Board.
  
  
• SMALLCNTR
  
  A simple Counter.
  
  
• DEBUG_CKT
  
  HDL-based macro containing the necessary logic to perform hardware debugging and readback using the Hardware Debugger.