The following subsections describe the basic requirements for running the tutorial.
In this tutorial, the following terms are used:
Throughout this tutorial, file names, project names, and directory names (paths) are specified in lower case, and the design is referred to as Watch.
The Xilinx Foundation Series package, Version 1.5, is required to perform this tutorial. The design requires that you have installed the XC4000E libraries and device files and are licensed for Foundation Express or Base Express. These options are selected by default in the install program for either Express configuration.
A Foundation Express license is required to access the Express Constraints GUI.
This tutorial assumes that the software is installed in the default location c:\fndtn\active. If you have installed the software in a different location, substitute your installation path for c:\fndtn\active.
The tutorial projects are optionally installed (as sample projects) in the c:\fndtn\active\projects directory when you install the Foundation Series software. If you have installed the software, but are not sure whether the tutorial projects were installed, check for directories named c:\fndtn\active\projects\wtut*. These directories contain the various tutorial files.
Refer to the “Setting Up the Foundation Tools” chapter for installation instructions. For even more detailed instructions, refer to the Foundation Series 1.5 Install and Release Document.
During the software installation, the WTUT_VHD and WTUT_VER directories are created within c:\fndtn\active\projects, and the tutorial files are copied into these directories. These directories contain incomplete versions of the design, done in VHDL and Verilog, respectively. You will complete the design in the tutorial. However, solutions projects with all completed input and output files are also provided. The following table lists the associated project
Directory | Description |
---|---|
WTUT_VHD | Incomplete Watch Tutorial - VHDL |
WTUT_VER | Incomplete Watch Tutorial - Verilog |
WATCHVHD | Solution for Watch - VHDL |
WATCHVER | Solution for Watch - Verilog |
.
The WATCHVHD and WATCHVER solution projects contain the design files for the completed tutorials, including HDL files and the bitstream file.To conserve disk space, some intermediate files are not provided. Do not overwrite any files in the solutions directories.
The WTUT_VHD and WTUT_VER projects contain incomplete copies of the tutorial design. You will create the remaining files when you perform the tutorial. As described in a later step, you have the option to copy the Watch project to another area and perform the tutorial in this new area if desired.
This tutorial has been prepared for both VHDL and Verilog designs. This document applies to both designs simultaneously, noting differences where applicable. You will need to decide which HDL language you would like to work through the tutorial when you open the project.
Figure 5.1 Getting Started Dialog Box |
You can either work within the project directory as it has been installed from the CD, or you can make a copy to work on. To make a working copy of the tutorial files, begin with an opened project and perform the following steps.
Whenever copying projects in Foundation, it is important to use the “Copy Project” feature in the Project Manager to ensure that the project's directory structure is kept intact.