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Using the Express Constraints Editor (Foundation Express Only)

Xilinx recommends that you let the automatic placement and routing program, PAR, define the pinout of your design. Pre-assigning locations to the pins can sometimes degrade the performance of the place-and-route tools. However, it is usually necessary, at some point, to lock the pinout of a design so that it can be integrated into a PCB (printed circuit board).

Define the initial pinout by running the place-and-route tools without pin assignments, then locking down the pin placement so that it reflects the locations chosen by the tools. Assign locations to the pins in the Watch design so that the design can function in a Xilinx demonstration board. Because the design is simple and timing is not critical, these pin assignments do not adversely affect the ability of PAR to place-and-route the design. For HDL-based designs, these pin assignments can be done in a User Constraints File (.UCF) or with the Express Constraints Editor. Although .UCF files are provided for this tutorial, you will assign the pin location constraints in the Express Constraints Editor.

  1. In the Express Constraint Editor, click the Import Constraints button. Select WATCHVHD.EXC or WATCHVER.EXC, depending on the language you are using. These files are located in the project directory.

    This file has been created for you. The only difference you should see between your initial constraints and the ones saved in the .EXC file is the set of pin locations under the Ports tab.

    You can save Constraint Editor settings for a design by selecting File Export Constraints. When this .EXC file is read in for a later synthesis run, all constraints are re-established in the GUI, as long as they can be matched to instances in the current version.

  2. Under the Paths tab, click in the box in Row 2 below the Req. Delay header (from All Input Ports to RC-oscout). Change the delay to 35. Under the Ports tab, the Input Delays for RESET and STRTSTOP have changed to 35, as these represent all the Pad to Setup delays.

    You can change the values of individual Input or Output Delays by clicking the value in the Ports tab and either editing the value there or using the pulldown tab to select a value or define a new one. Change the values on one of the output signals using one of these methods.

    Figure 5.14 Ports Tab Display

  3. Under the Paths tab, right click either RC-oscout or All Output Ports in the sixth row and select New Subpath. The Create/Edit Timing Subpath window opens.

    Give this new subpath a name, Sub_flops_to_out, and a Delay value, 30. On the left hand side, double click all four flip flops that contain the name /stopwatch/sixty/lsbcount/qout*, to determine the sources of this subpath. On the lower right hand side, use the filter to select the destinations. Type ONE* in the field and click the Select button. All the ports beginning with ONESOUT will be highlighted. Click OK to see your new subpath.

    NOTE

    Base Express users cannot access the Express Constraints Editor. Pin location constraints must therefore be defined in a UCF file, which Xilinx has provided. Select Implementation Implementation Options. Click the Browse button next to User Constraints and select BASE.UCF.

    Figure 5.15 Editing Subpath in the Express Constraints Editor

  4. Under the Ports tab, add the two final pin location in the Pad Loc column. Scroll to the right to see this column. RESET must be assigned to P28, and STRTSTOP must be assigned to P18. To reassign, click the box and enter the pin number (including the P).

    NOTE

    The remaining I/Os have pin assignments. This information is contained in the .exc file. which you imported in Step 1.

  5. Click OK to continue synthesis. Express now optimizes the design.

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