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Synchronous Debugging

Debugging offers a means for capturing the internal CLB output states and displaying them in waveforms like a simulator. The Hardware Debugger offers two types of debugging modes: Synchronous and Asynchronous.

This section describes the synchronous debugging mode. In the synchronous debugging mode, the Hardware Debugger gives you control over the system clock, allowing for a specified number of clocks between snapshots of the internal FPGA states. For a description on triggering snapshots asynchronously, see the“Asynchronous Debugging” section.

Before you can begin debugging your design, you must make sure that the cable is properly connected for synchronous debugging. This was not needed for the downloading and verifying section so it was skipped.

  1. Connect the CLKO to P13 of the XC4003E.

  2. Close switch SW3-7. This selects the external clock connection at P13.

To debug your design, you must setup the debugging mode, set the Trigger type, set the clock type, and include signals and signal groups in your display list.

Setting up the Synchronous Debugging Mode

To set the debugging mode, follow these steps.

  1. Select the Debug Synchronous Mode or click the following toolbar button.

    figures/synchdb.gif

  2. Select View Control Panel to activate the Debug Control Panel.

    The appropriate options are enabled in the Debug Control Panel as shown in the following figure.

    Figure 9.8 Debug Control Panel

  3. In the Debug Control Panel, click the Clocks button to display the CLKO Clock Settings dialog box.

    Figure 9.9 Clock Settings Dialog Box

    The Use Xchecker Clock option should already be set. If not, then select it. Use the default clock speed setting of 0.921 MHz for this example.

  4. In the Debug Control Panel, click the Triggers button to display the Synchronous Trigger Settings dialog box.

    Figure 9.10 Trigger Settings Dialog Box

  5. Select Immediately from the Trigger On pulldown menu.

  6. Click OK.

Specifying Signal Groups

The Watch design has two internal buses that represent the value of the seconds counter prior the HEX2LED conversion: ONES[3:0] and TENS[3:0]. These signals are divided or separated into their individual bits during the implementation phase.

NOTE

For HDL designs, the ONES and TENS signals may have been renamed by the compiler. In this case, use the ONESOUT and TENSOUT signals instead. These signals will have undergone HEX2LED conversion to encode the seconds counter values for the seven segment display. For these binary conversions, see the following table.

Table 9_6 HEX2LED Conversion

HEX [3:0]     (Binary)
LED [6:0]     Binary
        0                      (0000)
                         40                  (100  0000)
        1                      (0001)
                         79                  (111  1001)
        2                      (0010)
                         24                  (010  0100)
        3                      (0011)
                         30                  (011  0000)
        4                      (0100)
                         19                  (001  1001)
        5                      (0101)
                         12                  (001  0010)
        6                      (0110)
                         02                  (00  0010)
        7                      (0111)
                         78                  (111 1000)
        8                      (1000)
                         00                  (000  0000)
        9                      (1001)
                         18                  (001  1000)
        A                     (1010)
                         08                  (000  1000)
        B                     (1011)
                         03                  (000  0011)
        C                     (1100)
                         46                  (100  0110)
        D                     (1101)
                         21                  (010  0001)
        E                      (1110)
                         06                  (000  0110)
        F                      (1111)
                         0E                  (000  1110)

NOTE

For example, HEX [3:0] would be ONES[3:0] and LED[6:0] would be ONESOUT [6:0]. The counters only count up to 9 since they are designated to count in powers of ten. With this encoding, the seven-segment display LEDs are active low. In other words, for the output of HEX2LED, a `0' is “On”.

In the Hardware Debugger, these signals can be recombined into a bus format for a more convenient display.

To specify which signals to view, follow these steps to add signals to the list of signals to display.

  1. In the Debug Control Panel, click the Groups button to display the Signal Groups dialog box from which you can group signals into a bus for easy viewing.

    The Signal Groups dialog box appears as shown in the following figure.

    Figure 9.11 Signal Groups Dialog Box

  2. To create a new group, click New in the Groups group box. The Group Name box appears, as shown in the following figure.

    Figure 9.12 Group Name Dialog Box

  3. Type the name ones in the Group Name dialog box and click OK. The new group name appears in the Groups field of the Signal Groups dialog box. 

  4. In the Available Signals field, scroll until you see the signal names ONES<0> through ONES<3>. Select these signals and move them into the Grouped Signals field with the > button.

    NOTE

    If you are verifying the HDL design, select the ONESOUT<0> through ONESOUT<3> instead of ONES<0> through ONES<3>.

    Figure 9.13 Signal Groups Dialog Box (Schematic Design)

    Figure 9.14 Signal Groups Dialog Box (HDL Design)

    NOTE

    You can globally define the signals to display in the selection list box by typing the first characters of the signals followed by a wildcard character (*) in the Filter For Signals box and clicking Apply.

    The MSB (ONES<3>) needs to be at the top of the list with the rest descending sequentially. Select the signals as needed and use the Up and Down buttons to adjust their order in the list.

  5. When you are done specifying the group, click Save.

  6. Make another group for the TENS and add TENS3 through TENS0.

    NOTE

    If you are verifying the HDL design, select the TENSOUT<0> through TENSOUT<3> instead of TENS<0> through TENS<3>.

  7. Click Close when you are done adding groups.

Adding Signal Groups to Your Display List

In this section, you use the Display Signals dialog box to select the signals to view and debug. To add signals and the groups you just defined to your display list, follow these steps.

  1. In the Debug Control Panel, click Display to invoke the Display Signals dialog box.

  2. Use the Display Signals dialog box, shown in the following figure, to include the Signals TENTHSOUT<0> through TENTHSOUT<9> in the Displayed Signals field.

    Figure 9.15 Display Signals Dialog Box

  3. Click the Groups radio button in the Display group box to show the available signal groups that you just defined.

  4. Click the >> button to move the Available Signals to the Displayed Signals list.

  5. Click OK.

A new Waveform window appears with the selected signals for display.

Figure 9.16 Waveform Window

Reading the Device States

Now you can begin reading snapshots of the internal device states. You will adjust the number of clock cycles before each snapshot so that you can see the three buses independently transition appropriately.

  1. Initialize the counters so that they can begin counting. In the Debug Control Panel under Readback Control, click the Pulse/RESET button.

  2. In the Debug Control Panel, set the Number of Clocks to 1. Hold down the SPARE button on the demonstration board and click the Apply button once.

  3. In the Readback Control of the Debug Control Panel, set the Number of Snapshots to 10.

  4. Click the Read button.

    The Hardware Debugger now takes ten snapshots of the selected signal states incrementing the clock once between each snapshot.

    Figure 9.17 Waveform Window

  5. In the Synchronous Trigger Settings, increase the Number of Clock Cycles Before First Snapshot and Between Snapshots both to 10. Click OK.

  6. In the Readback Control of the Debug Control Panel, reduce the Number of snapshots to 9.

  7. Click the Read button.

    You now see the ONES bus cycling through its range of values in the waveform window.

    Figure 9.18 Waveform Window (Schematic Design)

    Figure 9.19 Waveform Window (HDL Design)

  8. In the Synchronous Trigger Settings, decrease the Number of Clock Cycles Before First Snapshot to 0 and between Snapshots to 1. Click OK.

  9. Decrease the Number of Snapshots in the Readback Control to 1.

  10. Increase the Number of Clocks in the Clock Control to 100. You can explicitly type in the desired number instead of scrolling for it.

  11. Click Apply.

  12. Click Read.

    The TENS bus now transitions. Repeat Steps 11 and 12 several times to observe the full values range of the TENS bus.

    Figure 9.20 Waveform Window (Schematic Design)

    Figure 9.21 Waveform Window (HDL Design)

The logical value of the displayed signals are shown in numerical form in the Cycle column. Click the portion of the waveform that you would like to see the numerical listing for, and the Cycle column automatically updates itself.

NOTE

To start fresh with the same waveform, click the right mouse button once. From the pop-up menu, select Clear All Waveforms. You will lose all unsaved data.

Changing the Signals Groups Radix

You may choose which radix you prefer your signals and groups to display in. The groups should have defaulted to HEX. To change to binary follow these steps.

  1. In the Waveform window, click the TENS groups.

  2. Select View Group Radix Binary.

    You may need to expand the Cycle column in order to view the value.

Saving and Closing the Waveform Window

When you are done with a debugging session and before exiting the waveform window, you can save it for future reference.

  1. Select File Close.

  2. Click Yes in the following pop-up box.

    Figure 9.22 Pop-up Dialog Box

  3. Select a name for the file and click Save.

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