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Asynchronous Debugging

In the previous section you used synchronous debugging to verify the operation of the counters in the Watch design. When the System clock connection for an application cannot be broken or otherwise interrupted, as you did in the Watch design with the Clock multiplexing, Asynchronous Debugging may be used in the absence of controlling the clock with the XChecker cable.

This section describes how to perform Asynchronous Debugging by setting up an external trigger to control snapshot timing.

Objective for this Section

The objective is to determine the encoding method used for the internal stopwatch state machine in the Watch design. Since this tutorial may be used with multiple design entry tutorials, including both schematic capture and HDL compilers, encoding schemes may vary.

The stopwatch state machine has six states shown in the following table.

Table 9_7 Stopwatch State Table

STATE
Description
Binary Code
CLEAR
Power-on initialization.

ZERO
Reset counters to 0.

START
Begin counting.

COUNT
Keep counting.

STOP
Stop counting.

STOPPED
Hold count value.


The Binary Code has been left blank for you to fill in.

Setting up the Demonstration Board

Before getting started, you must return the Watch design to use the internal oscillator and change some cable connections.

  1. Open SW3-7.

  2. Connect the TRIG flying (J10-1) lead to Pin 14 on the XC4003E device. There are two rows of pins adjacent to the left side of the XC4000E device. The row closest to the device contains the even number pins (12 through 32). Pin 14 is the second pin from the top in this row.

    Pin 14 of the FPGA conveniently provides an output of the internal clock. You can use this as a trigger. Any signal may be used for triggering as long as it represents a transition that you are interested in capturing. In this exercise, you want to capture the next state transition after changing an input logic level from the buttons and switches.

Setting up the Asynchronous Debugging Mode

To set the debugging mode, follow these steps.

  1. Select the Debug Asynchronous Mode or click the following toolbar button.

    figures/basyncdb.gif

    NOTE

    The Clock Control section of the Debug Control Panel is now disabled.

  2. Click the Triggers button in the Debug Control Panel.

    Now the Asynchronous Trigger Settings dialog box appears.

  3. Select Trigger On External. Click OK.

  4. Make a new Signal Group for the STOPWTCH state machine outputs. For a detailed description on making signal groups, return to the “Specifying Signal Groups” section.

    The name of the signals should be $$/STOPWTCH<0> and so on for bits <1> and <2>. The $$/ represents some arbitrary hierarchical name. Since this state machine exists below a macro in the design, randomly generated instance names for the macro may be placed by an HDL compiler into the total signal name.

    Do not be concerned about this. The STOPWTCH name should be unique; therefore select the closest match from the Available Signal list.

  5. Add the stopwtch signal group that you just made along with the RST_INT signal.

  6. Set the Number of Snapshots in the Readback Control to 2. Capturing two readbacks per state transition will tell you if you have captured an erroneous value caused by a timing glitch.

Capturing the State Machine

Follow these steps to capture and display the six states of the stopwatch state machine.

  1. Press the RESET button.

  2. Click Read in the Readback control.

  3. Click the STOPWATCH waveform itself inside the waveform window and note the value. This state is the CLEAR state.

  4. Press and hold the SPARE button. While still holding the SPARE button down, click Read.

  5. Click the new segment of the STOPWATCH waveform and note the value. This is the START state.

  6. Release the SPARE button and click Read again. Note the value of the new section of the waveform. This is the COUNT state.

  7. Again press and hold the SPARE button. Click Read while holding down the SPARE button. This is the STOP state.

  8. Release the SPARE button and Read again. This is the STOPPED state.

  9. Close switch SW3-8 and Read again. This is the ZERO state.

Now you have the encoding scheme for the internal state machine. Your waveform should look something like that shown in the following figure.

Figure 9.23 Asynchronous Debugging Waveform

For more information on using the Hardware Debugger, refer to the online DynaText document, Hardware Debugger Reference/User Guide.

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