In the fourth design flow, you make changes to the schematic of a design that has been previously implemented in an FPGA, with or without floorplanning. You must re-implement the design into the target device while making only minimal changes to the previous implementation. These changes could be one or more of the following.
If you used the Floorplanner to floorplan the original design, use the Floorplanner now to correlate the logic in that design with the new changes, and adjust the constraints information accordingly. Next, use the Floorplanner's output MFP file to constrain the design during the mapping and placement phases of the implementation.
For HDL users, incremental design change is more complex with HDL designs because the synthesis tools change symbol names whenever the compilation method changes. When applying a previous revision of your Floorplan to the newly synthesized revision, it may be necessary to constrain some or all of the previously floorplanned elements.
Figure 2.4 Incremental Design Change Design Flow |  |
