In the third design flow, iterative floorplanning, you enter the design using a schematic capture tool or HDL. Next, use the Floorplanner to constrain portions of the design. Then, run MAP and PAR to map, place, and route the design into the target FPGA.
Based on the results of the automatic place and route tools, you can modify the currently floorplanned logic or select another portion of the design to constrain. Run MAP and PAR again with the new floorplanner constraints.
In addition, you can make small modifications to the placement done by PAR. After copying the placement over to the Floorplan window, you can make small changes to the Floorplan and save the new fully-constrained FNF file. The Floorplan 
Constrain All From Placement command fully constrains the placement of the design and can be used to fix small performance problems, such as a few design elements that are not optimally placed.
Repeat this Floorplanner-to-MAP and PAR loop until you have achieved your performance goals for the design. Refer to the design flow in the following figure.
Note that the same NGD file is used throughout the design flow.
Figure 2.3 Iterative Floorplanning Design Flow |  |
