Analyzing PAR Placement

This procedure describes how to analyze the placement results that PAR generates. You must first run PAR to generate an NCD file with placement information.

1. Select File Update and read in the NCD and NGD files.
   
   
2. Select View Placement in order to display the Placement window.
   
   

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   NOTE

   If the Placement window is empty, this indicates that the NCD file used to generate the Floorplanner netlist did not contain placement information. Make sure that you have run PAR and selected File Update, specifying the placed NCD file.

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3. Examine the Placement window for the following potential problems.
   
   
   • BUFTs with common output enables that are not vertically aligned or cross over longlines midpoints
     
     
   • RAM that is misaligned so as to prevent control signals from being routed on longlines
     
     
   • RPMs, BUFTs, and other groups source and load nets are close together
     
     
   • Structured logic elements that cross longline splitters into another quadrant
     
     

Refer to the following figure. Note the positions of the dark-colored BUFTs on the left. The placement is inefficient because two different longlines are required for the output enable signal. These BUFTs are misaligned because they are in two columns, which require different longlines, and are split between two different quadrants, crossing longline midpoints. Now, look at the light-colored BUFTs on the right. These BUFTs represent proper alignment in the FPGA because the common output enable signals connect to same vertical longline.

Figure 4.7 BUFT Placement

The following figure illustrates flip-flop to BUFT alignment in the FPGA. The left half of the example shows ineffective placement; see how the ratsnest lines intersect. The right half of the example shows the proper alignment of the flip-flops and their associated BUFTs as indicated by the parallel ratsnest.

Figure 4.8 Flip-flop/BUFT Alignment Example

NOTE

For clarity, the flip-flops and BUFTs occupy two different tiles. Normally, you would place this logic in the same tile to minimize the length of the ratsnest.

The following figure shows an example of groups placed so that the source and load nets are in close proximity. In many cases, where there is sufficient routing resources, you want to place source and load nets close together.

Figure 4.9 Viewing Placed Logic Symbols Using the Ratsnest

NOTE

In the example, the middle group is the selected logic from which the ratsnest shows its source nets and load nets.

1. To see that PAR placed group symbols efficiently, select them from the Placement window or the Design Hierarchy window.
   
   
2. Step through the design, selecting critical groups, and using the Ratsnest to view the distance between selected groups and their sources and loads.
   
   The Floorplanner highlights the selected symbols in the Placement window.