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Analyzing PAR Placement for Timing Constraints

This procedure explains how to analyze the placement of floorplanned logic by PAR with respect to Timing Constraints. If you are using the Design Manager, follow the instructions in that section.

You should analyze the logic placement in the following sequence.

  1. Examine the PAR report for Timing Constraints that were not met.

  2. Use Timing Analyzer to find those Timing Constraints that were not met.

  3. Use the Floorplanner ratsnest to view the path.

  4. If sub-optimal placement is causing the timing constraints to fail, floorplanning constraints can be used to improve the placement of logic to shorten time delays.

  5. Rerun MAP and PAR with the new floorplanning constraints.

From the Design Manager

If you are running the Floorplanner from the Design Manager, follow these steps to analyze the placement with regard to your Timing Constraints.

  1. Select a routed implementation revision from the Project View.

  2. Open up the Report Browser in one of two ways.

  3. From the Report Browser, double-click on the Post Layout Timing Report icon.

  4. Examine the report for any missed Timing Constraints.

  5. If you find that there are missed Timing Constraints in your design, click the Timing Analyzer toolbox button in the Design Manager.

    This step opens the Timing Analyzer window that displays the report file.

  6. Select Analyze Timing Constraints in the Timing Analyzer window.

  7. Select File Save in the Timing Analyzer window to save the timing report.

Following is a portion of a sample TRCE report.

Data path myaddr21 to syn294866 contains 4 levels of logic:
Path starting from Comp: IOB.PAD

To  Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
IOB.I1 Tpid 1.089R myaddr21
myaddr21
my_addr21
CLB.G3 net (fanout=3) 2.984R my_addr21
CLB.Y Tilo 1.190R N279
syn295958
CLB.G4 net (fanout=4) 2.984R syn295958
CLB.X Tiho 1.959R syn294869
syn323918
syn294869
CLB.G1 net (fanout=2) 2.984R syn294869
CLB.K Tihck 1.640R syn294866
syn323905
my_next_state<3>
my_current_state<3>
-------------------------------------------------
Total (5.878ns logic, 8.952ns route) 14.830ns

Using Find and Ratsnest to Find Critical Nets

With the edited TRCE report, you can use the Floorplanner Find command to display the paths that need fixing.

  1. Select Edit Find in the Floorplanner window.

  2. In the Find dialog box, set the Type field to Nets. Turn Auto Goto on and Auto Select off.

  3. In the Find dialog box, type the name of the first net in the TRCE report into the Name field. In the above example, the first net (identified by the first occurrence of the word “net” in the Delay type column) is my_addr21.

  4. Click Find in the Find dialog box.

  5. In the Design Nets window an arrow appears next to the net specified in the Find dialog box. Select this net. The net is displayed in the Placement window.

  6. Repeat steps 3 through 5 for each net listed in the TRCE report. In the Design Nets window hold down the Control button when you select each additional net. This ensures that the previous nets remain selected.

    When done, the Placement window shows the full path described in the TRCE report.

    NOTE

    You can also identify nets that have long delays by looking at the TRCE report and searching for the net by name.

    The Floorplanner displays the ratsnest in red. The length of the ratsnest does not correlate to a specific time delay. However, by moving logic blocks to shorten the ratsnest, you can improve on the delays.

    The following figure shows the ratsnest for a failed Timing Constraint.

    Figure 4.10 Ratsnest of the Failed Timing Constraint Path in the Floorplan Window

    Now that you know where the routing delay is in the Floorplan window, you can manually move logic blocks to shorten the ratsnest and improve the routing delays to meet the Timing Constraint.

    The following figure shows the example design. Compare this figure with the previous one and see that the logic block has been repositioned to be closer to the IOB.

    Figure 4.11 Repositioned Logic in Floorplan Window

  7. Save the Floorplanner file.

  8. Rerun MAP and PAR with the new floorplan constraints to see whether the new placement meets the Timing Constraint in the design.

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