Aligning Symbols

This procedure explains how to align symbols. When you are placing logic in the Floorplan window, aligning symbols reduces unnecessary routing between the placed logic elements. You can use the ratsnest to see the alignment of the placed logic.

The following considerations are important when floorplanning the design.

• Align tristate buffer enable signals. By placing tristate buffers with common enable signals in the same column, PAR will utilize a single longline to connect all the enables to the source.
  
  
• Align clock enable signals. By placing flip-flops with common clock enables in the same column, PAR will utilize a single longline to connect all the clock enables to the source.
  
  
• If an enable is sourced by an I/O, place the IOBs close to the column in which the longline runs to minimize the routing required for connections to that longline.
  
  
• Use the Hierarchy Group By command to create groups of related logic for quicker placement into the floorplan. The following figure shows the Group By dialog box.
  
  

Figure 4.15 Group By Dialog Box

Perform the following steps to align logic symbols in the Floorplan window.

1. Prior to floorplanning, use the Hierarchy Group By command to make groups of flip-flops to tristate buffers.
   
   
2. Floorplan the groups of flip-flops to tristate buffers (if small enough) into the same quadrant in the Floorplan window.
   
   For additional details, refer to the “Analyzing PAR Placement” section.
   
   
3. Floorplan the IOBs such that they are aligned with the flip-flop to tristate buffer groups. Check the ratsnest in the Floorplan window to see the alignment of the placed logic.
   
   

The example design shown in the following figure contains 16 flip-flops, 12 IOBs, 16 BUFTs, and one BUFGP.

Figure 4.16 Example Design

The following figure shows the example design, floorplanned so that the logic symbols are aligned.

Figure 4.17 Properly Aligned Logic Symbols

The following figure shows a closer view of a part of the floorplanned design shown in the previous figure. Note the alignment of the nets sourced by IOBs $1N100 and $1N112. BUS3 is aligned to a horizontal longline.

Figure 4.18 Close-up of Aligned Logic Symbols