Floorplanning Incremental Schematic Changes

Xilinx defines incremental designing as making changes, at the design entry stage, to a design that has been previously implemented in an FPGA, with or without floorplanning. These changes can include the following.

Adding logic
Removing logic
Changing existing logic

The following procedure explains only how to make incremental changes when you have used the Floorplanner to floorplan the original design.

NOTE

This procedure may not work as well with HDL designs. Using the HDL coding tips in the Synopsys Synthesis and Simulation Design Guide will make incremental floorplanning on HDL designs easier.

Design Example

The schematic-based design has been floorplanned and a change in the design requires that you add some logic to the original schematic.

Make the necessary changes to the schematic design.

NOTE
Whenever you make changes to the schematic, you must run NGDBuild and MAP to regenerate a new mapped or placed NCD file.
Select File Update to open a file open dialog box.
Select the new NGD and NCD files to read in to the Floorplanner.

The Floorplanner reads in the design.ncd. Whenever an FNF file exists for the design, Floorplanner reads it in addition to reading the NGD and NCD files. The logic that was floorplanned is again placed into the same location in the Floorplan window.

The next three figures show the design example schematic, the design hierarchy of the NGD and NCD files, and the floorplanned design.

The following figure shows the original schematic of the design example.

Figure 4.29 Design Example

The following figure shows the design hierarchy of the example in the Design Hierarchy window.

Figure 4.30 Design Example Design Hierarchy

The following figure shows the floorplanned design example.

Figure 4.31 Floorplanned Design Example

The following figure shows the design example schematic that has been modified. A two-input AND gate, an OBUF, and an OPAD have been added to the design.

Figure 4.32 Changes to the Original Schematic

When the design is reloaded into the Floorplanner, the newly added logic appears in the Design hierarchy. In the following figure, two new symbols $1N57 [IOB] and $FG_SIG_OUT [FG] still remain in the hierarchy (as indicated by the logic symbol icon) and may be placed into the floorplan.