Iterative Floorplanning

This procedure explains how to floorplan your design iteratively. In this method, you manually place the structured logic of the design. Next, run MAP and PAR to automatically map and place the random logic of the design. Repeat this cycle of manual and automatic map and placement until you have placed the critical paths of the design in the FPGA floorplan.

Perform the following steps to floorplan iteratively.

1. Work with the most critical path first.
   
   
2. From this part of your design, floorplan the structured logic.
   
   
3. Select File Save to save the floorplan and generate an MFP file.
   
   
4. Run MAP and PAR, using the new MFP file, to obtain a placed design.
   
   

When PAR is done, select File Update to read the placed design file in the Floorplanner. You can either make changes to the original floorplan and repeat these steps, or move on to floorplanning more logic.