After a design has been mapped to a specific architecture, it is ready for placement and routing by PAR, Xilinx's Place and Route program. PAR reads an NCD (Native Circuit Description) file and automatically performs optimal placement and routing on the mapped CLBs and IOBs in the design.
PAR can be run in a timing driven mode, which means that placement and routing are executed according to timing constraints that you specify up front in the design process. The static timing analysis engine interacts with PAR to ensure that the timing constraints you impose on the design are met.
When PAR is complete, you can verify that the design's timing characteristics (relative to the PCF, or physical constraints file) have been met by running TRACE (Timing Reporter and Circuit Evaluator), Xilinx's timing verification and reporting utility. TRACE issues a detailed report showing any timing warnings and errors. See the “TRACE (Timing Reporter and Circuit Evaluator)” section for more information.
Each PAR iteration has a score attached to it based on factors such as the number of unrouted nets, the number of timing constraints not met, the average of all the maximum delays on all nets, and other factors - all weighted by their relative importance.
Input to PAR consists of the following files.
Output from PAR consists of the following files.
The following figure shows a diagram of the PAR design flow. For more information on the PAR program, see the “PAR - Place and Route” chapter of the Development System Reference Guide.
The Alliance M1.5 Software supports automatic pinlocking, which means that pad locations are written out into the UCF file.
Figure 3.4 PAR Flow |  |
