Chapter 2

Designing with CPLDs

This chapter discusses how to control various device features and get the best performance from Xilinx XC9500 and XC9500XL CPLDs. You can control aspects of design implementation at these points:

• in your VHDL or Verilog HDL source design
  
  
• using dc_shell commands or Design Analyzer commands
  
  
• using FPGA Express implementation options
  
  
• using cpld command-line parameters or the Xilinx Design Manager templates
  
  

For more information on synthesis library cells, see the "Library Component Specifications" appendix. For more information on attributes, see the "Attributes" appendix. For more information on CPLD commands, see chapter 3, Compiling and Fitting your Designs.

This chapter describes how you can control the aspects of design implementation. It contains the following sections:

• “Target Device Selection” section
  
  
• “Special I/O Ports” section
  
  
• “Controlling Register Initial State” section
  
  
• “Controlling Power Consumption” section
  
  
• “Controlling Output Slew Rate” section
  
  
• “Controlling the Pinout” section
  
  
• “Controlling Logic Optimization” section
  
  
• “Controlling Timing Paths” section
  
  
• “XC9000 Local Feedback” section