This section describes the procedure for compiling a complete CPLD design based on VHDL or HDL. If you are preparing a VHDL/HDL-based module for inclusion in a schematic-based design, refer to the section "Compiling Behavioral Modules for Schematics" later in this chapter.
The Synopsys compiler synthesizes your source design and creates an EDIF 2.0.0 netlist file composed of logic primitives that is used by the Xilinx CPLD fitter to implement your design in a CPLD. All compiler commands are executed from within the Synopsys dc_shell environment.
Enter the Synopsys dc_shell environment by entering the following Synopsys command on the UNIX command line:
dc_shell
You will see the dc_shell prompt.
To interpret your design and verify that it is free of errors, enter the following Synopsys command for VHDL designs:
analyze -format vhdl design_name.vhd
or, for Verilog HDL designs:
analyze -format verilog design_name.v
For example, the command used inVHDL version of the scan example in the "Getting Started with Xilinx CPLDs" chapter:
analyze -format vhdl scan.vhd
If your source file contains initial signal values (which are used only for functional simulation) they will cause warnings that can be safely ignored; these initial signal values are not used during synthesis. Actual register initial states are set using attributes, as described in Chapter 2.
If the analyze command finds errors, you will need to make the necessary corrections to your source file and repeat the analyze command before continuing with synthesis.
To derive a logical design, based on your VHDL/HDL description, enter the following Synopsys command:
elaborate entity_name
where entity_name is the name of your top-level entity in your design.
For example, the command used in the scan example in the "Getting Started with Xilinx CPLDs" chapter:
elaborate scan
During this step, the compiler displays information about all registers and 3-state buffers encountered in your design.
You are now ready to compile your design using the XC9000 target library.
When you compile your design, the Synopsys synthesizer uses the components in the Xilinx XC9000 technology library to create an actual logic implementation of your design. The library used during compilation is defined by the dc_shell target_library variable, typically specified in your .synopsys_dc.setup file.
To synthesize your design based on target CPLD technology library, enter the following Synopsys command:
compile [-map_effort low]
The mapping effort parameter is optional. However, it is recommended that you set it to LOW to save compilation time. The synthesizer does not perform any speed or area optimization for CPLD designs; this optimization is performed after compilation by the CPLD fitter.
Attributes are used to control the physical implementation of your design as described in Chapter 2. All attributes are optional. The attributes that you may want to set at this time are:
For example, the attributes used in the scan example in the "Getting Started with Xilinx CPLDs" chapter:
set_attribute END_REG* init -type string S
See the "Attributes" appendix for complete details on all supported attributes.
Now you must define which signals are connected to the physical I/O pins of the CPLD.
Use the following command to identify all ports in your design for which the synthesizer needs to infer an I/O buffer:
set_port_is_pad port_name
Do not use this command for any ports for which you instantiated I/O buffer cells from the library.
Normally, you would automatically place I/O buffer cells on all top-level ports in the design. Enter the following Synopsys command:
set_port_is_pad "*"
For the ports that were specified by set_port_is_pad, the following command infers the appropriate I/O buffer cells into your design:
insert_pads
If you want to control output slew rate or explicitly assign global buffers to input ports of your design, the dc_shell set_pad_type command must be invoked before the insert_pads command, as described in Special I/O Ports.
Before writing the netlist, you should flatten the hierarchy of your design. Any attribute or timing constraints attached to objects in any hierarchy levels below the top would be lost unless the design is flattened. Enter the following command to flatten your design:
ungroup -all -flatten
Write your synthesized design file in EDIF netlist format by entering the following Synopsys command:
write -format edif -hierarchy -output design_name.sedif
where:
For example, the command used in the scan example in the "Getting Started with Xilinx CPLDs" chapter:
write -format edif -hierarchy -output scan.sedif
If you specified any timing constraints for your design (in dc_shell), you must write them to a dc_shell script file so they can be read by the Xilinx software. Enter the write_script command and redirect its output to a file as follows:
write_script > design_name.dc
Your design must be flattened using the ungroup -all -flatten command before writing the script file.
This is the end of the required processing in dc_shell. Before exiting you may wish to save the design database in Synopsys db format by executing the write command. You can exit dc_shell by entering the following Synopsys command:
exit
If you specified any timing constraints for your design and wrote a dc_shell script file as in Step 9, you must translate the script file into a Xilinx constraint file (.ncf) that can be read by the fitter. Enter the dc2ncf command at the Unix prompt as follows:
dc2ncf design_name.dc
None of the Synopsys timing or area analysis reports are useful at this time because the CPLD technology libraries do not contain timing or area estimation data. The Xilinx fitter provides a Static Timing Report which shows the calculated worst case timing for each logic path in your design.
You are now ready to begin the fitting process as described in the next section.
