Fitting Your Design

Using Design Manager Interface

You can start the Design Manager from the command line by entering the following command:

dsgnmgr

Creating a New Project

After opening the Design Manager for the first time, you must create a new project for your design.

A project includes all design versions, implementation revisions, reports, and any other Xilinx data created while you work with a design. The Design Manager graphically displays information about these items in the project view. When you create a new project, you specify a design to open and a directory for the project. You can create as many projects as you want, but you can only work with one at a time.

The following procedure explains how to create a new project by importing a design.

1. Select File New Project from the Design Manager menu.
   
   The New Project dialog box appears, as shown in the “New Project Dialog Box” figure.
   
   

   Figure 3.1 New Project Dialog Box

2. Specify a design file to open using one of the following methods.
   
   
   • In the Input Design field, type the name of a design file to open.
     
     
   • Click on the Input Design Browse button to the right of the Input Design box. The Open dialog box appears. Select an SEDIF file to open. Click on OK.
     
     

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     NOTE

     The Design Manager automatically creates a subdirectory named xproj and appends it to the work directory. The Design Manager uses the xproj directory to store all the data files for the project. By default, the design directory is used as the work directory; however, you can change the default directory by typing a path in the Work Directory field or by using Browse to select a directory.

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3. In the New Project dialog box, click OK.
   
   After your design has loaded, the Design Manager window appears, configured for the loaded design.
   
   

To Implement a Design

The following procedure describes how to implement a design automatically from the Design Manager.

1. Select Design Implement from the Design Manager menu.
   
   The Implement dialog box appears, as shown in the “Implement Dialog Box” figure. The options in this dialog box are described in the Design Manager/Flow Engine Reference/User Guide.
   
   

   Figure 3.2 Implement Dialog Box

2. In the Implement dialog box, click on the Select button to the right of the Part text field.
   
   The Part Selector appears, as shown in the “Part Selector Dialog Box” figure.
   
   

   Figure 3.3 Part Selector Dialog Box

3. Select the family, device, package, and speed grade.
   
   By default, the CPLD fitter automatically selects the device, package and speed for you. You can select any specific device, package or speed, or leave any of these boxes as “All.”
   
   For a specific explanation of each option, see the Design Manager/Flow Engine Reference/User Guide.
   
   
4. Click on OK to set the part type.
   
   
5. To set design implementation options, click on the Options button in the Implement dialog box.
   
   The Options dialog box appears, as shown in the “Options Dialog Box” figure.
   
   

   Figure 3.4 Options Dialog Box

6. Select desired options, such as templates to use and reports to generate.
   
   For a specific explanation of each option see the Design Manager/Flow Engine Reference/User Guide. The “Implementation Options” chapter discusses all implementation options for the XC9500 and XC9500XL CPLD families, including Simulation Data Options.
   
   
7. Click on OK to set the options.
   
   
8. In the Implement dialog box, enter a version and revision name if you want to change the default names.
   
   
9. Click on the Run button to implement the design.
   
   The Flow Engine window appears. When processing is complete, the Flow Engine closes and the Implementation Status dialog box, shown in the “Implementation Status Dialog Box” figure, appears.
   
   

   Figure 3.5 Implementation Status Dialog Box

10. In the Implementation Status dialog box, click on Reports to view the reports generated by the Flow Engine or click on View Logfile to view the implementation logfile.
    
    

NOTE

At this point you can also perform timing simulation and program the device. Timing simulation is described in the Interface User Guide for your system. Device programming is described in the JTAG Programmer Guide.

Using Unix Command Line

The cpld command is used to invoke the Xilinx CPLD fitter software. CPLD uses the logical design produced by the Synopsys compiler to create a physical layout for a target CPLD.

To invoke the fitter, enter the following Xilinx command on the UNIX command line:

cpld [options] design_name

Invoking the cpld command with no parameters produces a listing of all available command-line options.

The design_name is the name of the netlist file produced by the Synopsys compiler, without path qualifiers, and either with or without the extension, .sedif.

If design_name is specified without extension, the cpld command automatically searches for and reads the netlist with file extension .sedif as produced by Synopsys FPGA Compiler and Design Compiler. The cpld command also accepts files with extensions .edif, .edn, .xnf, .sxnf and .pld. If you happen to have any files with the same name as your design and with one of these other extensions, you should remove them from your design directory before running the cpld command to prevent the wrong file from being read inadvertently.

If you do not specify any optional parameters, the fitter automatically selects a device from the XC9500 family which fits your design (if possible).

The cpld command performs the following functions:

• Reads the netlist file (design_name.sedif) produced by the Synopsys compiler.
  
  
• If you specified timing constraints for your design and saved them in a dc_shell script file (design_name.dc), the cpld fitter automatically reads the .dc file, translating it first into a Xilinx netlist constraint file (design_name.ncf).
  
  
• Minimizes and collapses the combinational logic of your design so that it requires the least number of macrocell and product term resources.
  
  
• Partitions and maps your design to fit within the architecture of the CPLD, optionally selecting the target device.
  
  
• Creates a device programming file (design_name.jed).
  
  
• Creates a fitter report (design_name.rpt) that shows you information such as the type and quantity of device resources used, and the resulting pinout.
  
  
• Creates a Static Timing Report (design_name.tim) that shows the calculated worst-case timing for all signal paths in your design.
  
  
• Creates a guide file (design_name.gyd) that is used to lock signal names to device pins, allowing you to keep the device pinouts during subsequent design iterations.
  
  
• Creates a timing simulation database file (design_name.nga) that can be translated into structural VHDL (for the Synopsys VSS or other VITAL-compliant simulator) or structural Verilog.
  
  

Whenever the cpld command is invoked, it copies any existing fitter report file (.rpt), timing report file (.tim), guide file (.gyd), and programming file (.jed) to a subdirectory named "backup.".

CPLD Command Parameters

The [options] field of the cpld command represents an optional list of one or more command-line parameters. The following are the cpld command-line parameters that apply to Synopsys design entry:

• -autopwrslew - reduces macrocell power mode after meeting timing specifications.
  
  
• -autoslewpwr - reduces slew rate and then power mode to meet timing specifications.
  
  
• -detail - produces a detailed path timing report (design_name.tmd) in addition to the default summary report (design_name.tim).
  
  
• -grounds - creates programmable ground pins on unused I/O ports.
  
  
• -ignoreloc - temporarily ignores all LOC attributes in the design, allowing the fitter to assign the locations of all I/O pins.
  
  
• -ignorets - temporarily ignores all timing specifications in the design_name.ncf or UCF file.
  
  
• inputs <n> - sets collapsing input limit per macrocell function (default is 36 input signals).
  
  
• -localfbk - uses local feedback to improve timing when possible (XC9500 only, except XC9536). Default is to use local feedback only when needed to meet timespecs.
  
  
• -loweffort - specifies low fitting effort.
  
  
• -lowpwr - set the default power mode to low for all macrocells in the design (default is standard power).
  
  
• -nodt - disables automatic transformation between D-type and T-type macrocell registers.
  
  
• -nogck - disables global clock optimization.
  
  
• -nogsr - disables global set/reset optimization.
  
  
• -nogts - disables global output-enable (GTS) optimization.
  
  
• -nomlopt - disables multi-level logic optimization.
  
  
• -nota - bypasses the timing analyzer so that no summary static timing report (design_name.tim) is generated.
  
  
• -notsim - prevents generation of timing simulation database file (design_name.nga).
  
  
• -notiming - inhibits the default global timing optimization performed by the fitter; only paths with timing specifications are optimized to improve timing.
  
  
• -nouim - disables formation of “wire-and” functions in the FastCONNECT structure of XC9500 devices.
  
  
• -noxor - disables factorization and transformation between pure sum-of-products logic and logic using macrocell XOR-gate.
  
  
• -p part_type - specifies the target CPLD device type or set of devices from which to choose (default is automatic device selection from the XC9500 family); where part_type can be:
  
  
  • 9500 = any XC9500 family device (auto selection)
    
    
  • 9500xl = any XC9500XL family device (auto selection)
    
    
  • “95ddd[xl][-ss][-pppp]” - where 95ddd is the device code (such as 95108), ss is the speed grade, pppp is the package code (such as PQ160), and an asterisk (*) can be used as a wildcard string (quotes required around part_type when asterisk is used). You must include the device code suffix “xl” to select any devices from the XC9500XL family. For example, “95*xl-*-pc*” selects any XC9500XL device in a pc-type package.
    
    
• -pinfbk - uses pin feedback to improve timing when possible.
  
  
• -pinlock - uses the guide file (design_name.gyd) from the last successful invocation of the fitter to reproduce the same pin locations (default is automatic pin assignment).
  
  
• -pterms nn - sets the limit to nn for the number of product terms allowed as a result of collapsing (default=20).
  
  

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  NOTE

  If you have complex combinational logic in your design, such as state machines, comparators, etc., you may need to specify the -pterms option with a limit higher than 20 to achieve higher performance results. Refer to the Controlling Logic Optimization section in Chapter 2 for information.

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• -s signature - specifies the user signature string to be programmed into the device for identification purposes, where signature is a string of 1-4 alphanumeric characters (default is the design name truncated to 4 characters).
  
  
• -slowslew - sets the default output slew-rate to slow (default is normally fast).
  
  
• -ucf file_name - reads user constraints from file_name.ucf file (by default, the fitter reads design_name.ucf if it exists).
  
  
• -xactfit - Use this option only if you have a design implemented in XACT v6 and cannot get the same pinout using the current software. If this is not used, advanced fitting is used as default.