If you are developing a schematic-based design using some other schematic entry tool (such as Viewlogic or Mentor), you can include module symbols in your schematic that are functionally defined using Synopsys VHDL or Verilog HDL. These are called "behavioral modules".
This section describes how to prepare a synthesis-based behavioral module using Synopsys FPGA Compiler or Design Compiler. Behavioral modules are represented by custom symbols in the schematic design. In general, the names of the pins on your behavioral module symbol should match the names of the top-level entity ports in your Synopsys source file. Refer to the Schematic Design Guide for information on how to include the behavioral module symbol in your schematic design.
The procedure for compiling a behavioral module is similar to the procedure for compiling a complete CPLD design, as described earlier in this chapter. For behavioral modules, however, you do not specify device I/O pads; you would therefore omit the set_port_is_pad and insert_pads commands. Also, many of the dc_shell attributes, such as LOC, are not applicable to behavioral modules.
Behavioral modules are compiled and written as EDIF netlists by performing the following steps:
Enter the Synopsys dc_shell environment by entering the following Synopsys command on the UNIX command line:
dc_shell
You will see the dc_shell prompt.
To interpret your synthesis module and verify that it is free of errors, enter the following Synopsys command for VHDL modules:
analyze -format vhdl module_name.vhd
or, for Verilog HDL modules:
analyze -format verilog module_name.v
If your source file contains initial signal values (which are used only for functional simulation) they will cause warnings that can be safely ignored; these initial signal values are not used during synthesis. Actual register initial states are set using attributes, as described in Chapter 2.
If the analyze command finds errors, you will need to make the necessary corrections to your source file and repeat the analyze command before continuing with synthesis.
To derive a logical design, based on your VHDL/HDL description, enter the following Synopsys command:
elaborate entity_name
where entity_name is the name of your top-level entity in your module.
During this step, the compiler displays information about all registers and 3-state buffers encountered in your module.
You are now ready to compile your module using the XC9000 synthesis.
When you compile your module, the Synopsys synthesizer uses the components in the Xilinx XC9000 technology library to create an actual implementation of your module. The library used during compilation is defined by the dc_shell target_library variable, typically specified in your .synopsys_dc.setup file.
To synthesize your module based on target CPLD technology library, enter the following Synopsys command:
compile [-map_effort low]
The mapping effort parameter is optional. However, it is recommended that you set it to LOW to save compilation time. The synthesizer does not perform any speed or area optimization for CPLD designs; this optimization is performed after compilation by the CPLD fitter.
The only attribute that you may set for behavioral modules is: Register initial states
For example:
set_attribute Q_REG init -type string S
If you set any attributes on design objects in any hierarchy levels below the top level, you must flatten the design so that your attributes get written to the EDIF netlist. Enter the following command to flatten your deign:
ungroup -all -flatten
Write your synthesized module file in EDIF netlist format by entering the following Synopsys command:
write -format edif -hierarchy -output module_name.sedif
where:
The EDIF file produced by the Compiler will be read when the fitter finds the behavioral module symbol in your schematic design.
