This package defines the IEEE standard for designers to use when describing the interconnection data types used in VHDL modeling. The logic system defined in this package might be insufficient for modeling switched transistors, because such a requirement is out of the scope of this effort. Furthermore, mathematics, primitives, and timing standards are considered orthogonal issues as they relate to this package and are beyond the scope of this effort.
The std_logic_1164 package contains Express synthesis directives. One function, however, is not currently supported for synthesis; is_x.
To use this package in a VHDL source file, include the following lines at the top of the source file.
library IEEE;
use IEEE.std_logic_1164.all;When you analyze your VHDL source file, Foundation Express automatically finds the IEEE library and the std_logic_1164 package. However, you must analyze the use packages not contained in the IEEE and Synopsys libraries before processing a source file that uses them.
