Chapter 10

VHDL Packages

Three VHDL packages are included with this release. These packages are a combination of standard IEEE packages and Synopsys packages that have been added to the standard IEEE package. Synopsis-specific changes were made to these packages before including them into the IEEE packages. This chapter discusses the contents of each package. Each section of this chapter explains one of these packages.

• “std_logic_1164 Package”
  
  Defines a standard for designers to use when describing the interconnection data types used in VHDL modeling
  
  
• “std_logic_arith Package”
  
  Provides a set of arithmetic, conversion, and comparison functions for SIGNED, UNSIGNED, INTEGER, STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR types
  
  
• “std_logic_misc Package”
  
  

Defines supplemental types, subtypes, constants, and functions for the std_logic_1164 package