VHDL Construct Support
A construct can be fully supported, ignored, or unsupported. Ignored and unsupported constructs are defined as follows.
- Ignored means that the construct is allowed in the VHDL source but is ignored by Foundation Express.
- Unsupported means that the construct is not allowed in the VHDL source and that Foundation Express flags the construct as an error. If errors are found in a VHDL description, the description is not translated (synthesized).
Constructs are listed in the following order.
- Design units
- Data types
- Declarations
- Specifications
- Names
- Operators
- Operands and expressions
- Sequential statements
- Concurrent statements
- Predefined language environment
Design Units
- Entity
The entity statement part is ignored.
Generics are supported, but only of type INTEGER.
Default values for ports are ignored.
The keyword end may be followed by the keyword entity.
An example follows.
entity HALFADD is
port (A,B : in bit;
SUM, CARRY : out bit);
end entity HALFADD;
- Architecture
Multiple architectures are allowed.
Global signal interaction between architectures is unsupported.
The keyword end may be followed by the keyword architecture. An example follows.
architecture EX2 of CONC is
signal Z,A,B,C,D :
integer;
begin
Z<= C = D;
D,= A = B;
end architecture EX2;
- Configuration
Configuration declarations and block configurations are supported but only to specify the top-level architecture for a top-level entity.
Attribute specifications, use clauses, component configurations, and nested block configurations are unsupported.
The keyword end may be followed by the keyword configuration. An example follows.
configuration CFG_FULLADD of FULLADD is
for STRUCTURAL
for all : HALFADD use entity
work.HALFADD (BEHAVE);
end for;
end for;
end configuration CFG_FULLADD;
- Package
Packages are fully supported.
The keyword end may be followed by the keyword package. An example follows.
package P is
constant C : integer;
end package P;
- Package body
The keyword end may be followed by the keyword package body. An example follows.
package P is
constant C : integer;
end P
package body P is
constant C : integer := 200;
end package body P;
- Library
Libraries and separate compilation are supported.
- Subprogram
Default values for parameters are unsupported. Assigning subprograms to indexes and slices of unconstrained out parameters is unsupported, unless the actual parameter is an identifier.
Subprogram recursion is unsupported if the recursion is not bounded by a static value.
Resolution functions are supported for wired-logic and three-state functions only.
Subprograms can only be declared in packages and in the declaration part of an architecture.
Data Types
- Enumeration
Enumeration is fully supported.
- Integer
Infinite-precision arithmetic is unsupported.
Integer types are automatically converted to bit vectors whose width is as small as possible to accommodate all possible values of the type's range, either in unsigned binary for nonnegative ranges or in 2s-complement form for ranges that include negative numbers.
- Physical
The end units construct is supported. An example follows.
type DURATION is range-1E18 to 1E18
units
fs; -- femtosecond
ps = 1000 fs; -- picosecond
ns = 1000 ps; -- nanosecond
us = 1000 ns; -- microsecond
ms = 1000 us; -- millisecond
sec = 1000 ms; -- second
min = 60 sec; -- minute
end units;
- Floating
Floating-point type declarations are ignored. The use of floating-point types is unsupported except for floating-point constants used with Express-defined attributes. (See the chapter “Foundation Express Compiler Directives”.)
- Array
Array ranges and indexes other than integers are unsupported.
Multidimensional arrays are unsupported, but arrays of arrays are supported.
- Record
Record data types are fully supported.
The keywords end record may be followed by the type name. An example follows.
type T_PACKET is record
BYTE_ID: std_ulogic;
PARITY : std_ulogic;
ADDRESS: integer range 0 to 3;
DATA : std_ulogic_vector (3 downto 0);
end record T_PACKET;
- Access
Access type declarations are ignored, and the use of access types is unsupported.
- File
File type declarations are ignored, and the use of file types is unsupported.
- Incomplete type declarations
Incomplete type declarations are unsupported.
Declarations
- Constant
Constant declarations are supported except for deferred constant declarations.
- Signal
Register and bus declarations are unsupported.
Resolution functions are supported for wired and three-state functions only.
Only declarations from a globally static type are supported.
Initial values are unsupported.
- Variable
Only declarations from a globally static type are supported.
Initial values are unsupported.
- File
File declarations are unsupported.
- Interface
Buffer and linkage are translated to out and inout, respectively.
- Alias
All objects can be aliased (signals, files, variables, and constants).
All nonobjects can also be aliased, except labels, loop parameters, and generate parameters. An example follows.
--an alias of a type
alias MY_LOGIC is ieee.std_logic_1164.std_logic;
--an alias of a component
alias NAND2 is ASIC_LIB.ONE_MICRON.ND2;
- Component
Only component declarations that list a valid entity name are supported.
The component name may be followed by the keyword is.
The keywords end component may be followed by a repetition of the component name. An example follows.
component component_name is
port (port list);
end component component_name;
- Attribute
Attribute declarations are fully supported. However, the use of user-defined attributes is unsupported.
Specifications
- Attribute
Others and all are unsupported in attribute specifications.
User-defined attributes can be specified, but the use of user-defined attributes is unsupported.
- Configuration
Configuration specifications are unsupported.
- Disconnection
Disconnection specifications are unsupported.
Attribute declarations are fully supported. However, the use of user-defined attributes is unsupported.
Names
- Simple
Simple names are fully supported.
- Selected
Selected (qualified) names outside of a use clause are unsupported.
Overriding the scopes of identifiers is unsupported.
- Operator symbols
Operator symbols are fully supported.
- Indexed
Indexed names are fully supported with one exception. Indexing an unconstrained out parameter in a procedure is unsupported.
- Slice
Slice names are fully supported with one exception. Using a slice of an unconstrained out parameter in a procedure is unsupported unless the actual parameter is an identifier.
Array slices with others is supported. An example follows.
bus (5 downto 2)<=(others => `0');
- Attribute
Only the following predefined attributes are supported; base, left, right, high, low, range, reverse_range, and length.
The event and stable attributes are supported only as described with the wait and if statements. (See the “Sequential Statements” chapter.)
User-defined attribute names are unsupported.
The use of attributes with selected names (name.name'attribute) is unsupported.
Operators
- Logical
Logical operators are fully supported.
- Relational
Relational operators are fully supported.
- Addition
Concatenation and arithmetic operators are both fully supported.
- Signing
Signing operators are fully supported.
- Multiplying
The * (multiply) operator is fully supported.
The / (division), mod, and rem operators are supported only when both operands are constant or when the right operand is a constant power of 2.
- Miscellaneous
The ** operator is supported only when both operands are constant or when the left operand is 2.
The abs operator is fully supported.
- Operator overloading
Operator overloading is fully supported.
- Short-circuit operations
The short-circuit behavior of operators is not supported.
Operands and Expressions
- Based literals
Based literals are fully supported.
- Bit-vector literals
Bit_vector literals may be expressed in binary, octal, or hexadecimal. An example follows.
B”101”, O”31”, H”A
- Null literals
Null slices, null ranges, and null arrays are unsupported.
- Physical literals
Physical literals are ignored.
- Strings
Strings are fully supported.
- Aggregates
The use of types as aggregate choices is unsupported.
Record aggregates are unsupported.
- Function calls
Function conversions on input ports are not supported, because type conversions on formal ports in a connection specification are unsupported.
- Qualified expressions
Qualified expressions are fully supported.
- Type conversion
Type conversion is fully supported.
- Allocators
Allocators are unsupported.
- Static expressions
Static expressions are fully supported.
- Universal expressions
Floating-point expressions are unsupported, except in a Express-recognized attribute definition.
Infinite-precision expressions are not supported.
Precision is limited to 32 bits; all intermediate results are converted to integer.
Sequential Statements
Concurrent Statements
- Block
Guards on block statements are unsupported.
Ports and generics in block statements are unsupported.
The keyword block (or the guard condition, if there is one), may be followed by the keyword is. An example follows.
label: block (optional_guard_condition) is
--etc.
- Process
Sensitivity lists in process statements are ignored.
The keyword process (or the sensitivity list, if there is one) may be followed by the keyword is. An example follows.
[label:] process [(sensitivity-list)] is
- Concurrent procedure call
Concurrent procedure call statements are fully supported.
- Concurrent assertion
Concurrent assertion statements are ignored.
- Concurrent signal assignment
The guarded and transport keywords are ignored. Multiple waveforms are unsupported.
Any signal assignment statement may have an optional label. An example follows.
label: s0<=a and b;
- Component instantiation
Type conversion on the formal port of a connection specification is unsupported.
The component keyword used in instantiation is supported. An example follows.
architecture STRUCT of INC is
signal X, Y, S, C : bit;
component HALFADD
port (A, B : in bit;
SUM, CARRY : out bit);
end component;
begin
U1: HALFADD port map (X, Y, S, C);
-- other statements
end STRUCT;
- Generate
Block declarations are fully supported. An example follows.
GEN:
block begin
L1: CELL port map ( TOP, BOTTOM, A(0), B(0) );
L2: for I in 1 to 3 generate
L3: for J in 1 to 3 generate
L4: if I + J > 4 generate
L5: CELL port map (A(I-1), B(J-1), A(I), B(I) ));
end generate;
end generate;
end generate
end block GEN;
Predefined Language Environment
- Rising_edge, falling_edge
The rising_edge and falling_edge constructs are newly supported with this release. These constructs can be used as shorthand when you describe the rising edge event of a clock signal or the falling edge event of a clock signal.
- Severity_level type
The severity_level type is unsupported.
- Time type
The time type is unsupported.
- Now function
The now function is unsupported.
- TEXTIO package
The TEXTIO package is unsupported.
- Predefined attributes
Predefined attributes are unsupported, except for base, left, right, high, low, range, reverse_range, and length.
The event and stable attributes are supported only in the if and wait statements, as described in the “Sequential Statements” chapter.
The `image(literal) attribute is newly supported with this release. It is a string representation of an enumeration literal.
