The following words are reserved for the VHDL language and cannot be used as identifiers.
| abs | file | out |
| access | for | package |
| after | function | port |
| alias | generate | procedure |
| all | generic | process |
| and | guarded | range |
| architecture | if | record |
| array | in | register |
| assert | inout | rem |
| attribute | is | report |
| begin | label | return |
| block | library | select |
| body | linkage | severity |
| buffer | loop | signal |
| bus | map | subtype |
| case | mod | then |
| component | nand | to |
| configuration | new | transport |
| constant | next | type |
| disconnect | nor | units |
| downto | not | until |
| else | of | variable |
| elsif | on | wait |
| end | open | when |
| entity | or | while |
| exit | others |